1 files changed, 18 insertions, 128 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 43b48a0ab..ff5830822 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -31,8 +31,11 @@
 #ifndef __ARCH_ALPHA_REGFILE_HH__
 #define __ARCH_ALPHA_REGFILE_HH__
 
-#include "arch/alpha/types.hh"
 #include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/floatregfile.hh"
+#include "arch/alpha/intregfile.hh"
+#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/types.hh"
 #include "sim/faults.hh"
 
 #include <string>
@@ -45,111 +48,6 @@ class ThreadContext;
 namespace AlphaISA
 {
 
-    static inline std::string getIntRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getFloatRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getMiscRegName(RegIndex)
-    {
-        return "";
-    }
-
-    class IntRegFile
-    {
-      protected:
-        IntReg regs[NumIntRegs];
-
-      public:
-
-        IntReg readReg(int intReg)
-        {
-            return regs[intReg];
-        }
-
-        Fault setReg(int intReg, const IntReg &val)
-        {
-            regs[intReg] = val;
-            return NoFault;
-        }
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-        void clear()
-        { bzero(regs, sizeof(regs)); }
-    };
-
-    class FloatRegFile
-    {
-      public:
-
-        union {
-            uint64_t q[NumFloatRegs];	// integer qword view
-            double d[NumFloatRegs];	// double-precision floating point view
-        };
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-        void clear()
-        { bzero(d, sizeof(d)); }
-    };
-
-    class MiscRegFile {
-      protected:
-        uint64_t	fpcr;		// floating point condition codes
-        uint64_t	uniq;		// process-unique register
-        bool		lock_flag;	// lock flag for LL/SC
-        Addr		lock_addr;	// lock address for LL/SC
-
-      public:
-        MiscReg readReg(int misc_reg);
-
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault,
-                ThreadContext *tc);
-
-        //These functions should be removed once the simplescalar cpu model
-        //has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
-        Fault setReg(int misc_reg, const MiscReg &val);
-
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                ThreadContext *tc);
-
-        void clear()
-        {
-            fpcr = uniq = 0;
-            lock_flag = 0;
-            lock_addr = 0;
-        }
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-#if FULL_SYSTEM
-      protected:
-        typedef uint64_t InternalProcReg;
-
-        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-      private:
-        InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
-
-        Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-#endif
-        friend class RegFile;
-    };
-
     class RegFile {
 
       protected:
@@ -215,22 +113,20 @@ namespace AlphaISA
             return miscRegFile.readReg(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ThreadContext *tc)
+        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
         {
-            fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+            return miscRegFile.readRegWithEffect(miscReg, tc);
         }
 
-        Fault setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscReg(int miscReg, const MiscReg &val)
         {
-            return miscRegFile.setReg(miscReg, val);
+            miscRegFile.setReg(miscReg, val);
         }
 
-        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
@@ -253,26 +149,24 @@ namespace AlphaISA
             return readFloatRegBits(floatReg);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val)
+        void setFloatReg(int floatReg, const FloatReg &val)
         {
             floatRegFile.d[floatReg] = val;
-            return NoFault;
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        void setFloatReg(int floatReg, const FloatReg &val, int width)
         {
-            return setFloatReg(floatReg, val);
+            setFloatReg(floatReg, val);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
             floatRegFile.q[floatReg] = val;
-            return NoFault;
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
         {
-            return setFloatRegBits(floatReg, val);
+            setFloatRegBits(floatReg, val);
         }
 
         IntReg readIntReg(int intReg)
@@ -280,9 +174,9 @@ namespace AlphaISA
             return intRegFile.readReg(intReg);
         }
 
-        Fault setIntReg(int intReg, const IntReg &val)
+        void setIntReg(int intReg, const IntReg &val)
         {
-            return intRegFile.setReg(intReg, val);
+            intRegFile.setReg(intReg, val);
         }
 
         void serialize(std::ostream &os);
@@ -298,10 +192,6 @@ namespace AlphaISA
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-#if FULL_SYSTEM
-    void copyIprs(ThreadContext *src, ThreadContext *dest);
-#endif
 } // namespace AlphaISA
 
 #endif