1 files changed, 3 insertions, 118 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index e806adbcb..ff5830822 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -32,7 +32,9 @@
 #define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/ipr.hh"
+#include "arch/alpha/floatregfile.hh"
+#include "arch/alpha/intregfile.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "arch/alpha/types.hh"
 #include "sim/faults.hh"
 
@@ -46,119 +48,6 @@ class ThreadContext;
 namespace AlphaISA
 {
 
-    static inline std::string getIntRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getFloatRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getMiscRegName(RegIndex)
-    {
-        return "";
-    }
-
-    class IntRegFile
-    {
-      protected:
-        IntReg regs[NumIntRegs];
-
-      public:
-
-        IntReg readReg(int intReg)
-        {
-            return regs[intReg];
-        }
-
-        Fault setReg(int intReg, const IntReg &val)
-        {
-            regs[intReg] = val;
-            return NoFault;
-        }
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-        void clear()
-        { bzero(regs, sizeof(regs)); }
-    };
-
-    class FloatRegFile
-    {
-      public:
-
-        union {
-            uint64_t q[NumFloatRegs];	// integer qword view
-            double d[NumFloatRegs];	// double-precision floating point view
-        };
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-        void clear()
-        { bzero(d, sizeof(d)); }
-    };
-
-    class MiscRegFile {
-      protected:
-        uint64_t	fpcr;		// floating point condition codes
-        uint64_t	uniq;		// process-unique register
-        bool		lock_flag;	// lock flag for LL/SC
-        Addr		lock_addr;	// lock address for LL/SC
-        int		intr_flag;
-
-      public:
-        MiscRegFile()
-        {
-#if FULL_SYSTEM
-            initializeIprTable();
-#endif
-        }
-
-        MiscReg readReg(int misc_reg);
-
-        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
-
-        //These functions should be removed once the simplescalar cpu model
-        //has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
-        void setReg(int misc_reg, const MiscReg &val);
-
-        void setRegWithEffect(int misc_reg, const MiscReg &val,
-                ThreadContext *tc);
-
-        void clear()
-        {
-            fpcr = uniq = 0;
-            lock_flag = 0;
-            lock_addr = 0;
-            intr_flag = 0;
-        }
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-#if FULL_SYSTEM
-      protected:
-        typedef uint64_t InternalProcReg;
-
-        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-      private:
-        InternalProcReg readIpr(int idx, ThreadContext *tc);
-
-        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-#endif
-        friend class RegFile;
-    };
-
     class RegFile {
 
       protected:
@@ -303,10 +192,6 @@ namespace AlphaISA
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-#if FULL_SYSTEM
-    void copyIprs(ThreadContext *src, ThreadContext *dest);
-#endif
 } // namespace AlphaISA
 
 #endif