1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 08166bc6e..e28f260ea 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -114,7 +114,7 @@ class TLB : public BaseTLB
         return unimplBits == 0 || unimplBits == VAddrUnImplMask;
     }
 
-    static Fault checkCacheability(RequestPtr &req, bool itb = false);
+    static Fault checkCacheability(const RequestPtr &req, bool itb = false);
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
@@ -137,17 +137,18 @@ class TLB : public BaseTLB
     }
 
   protected:
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
 
   public:
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req, ThreadContext *tc,
+            Mode mode) const override;
 };
 
 } // namespace AlphaISA