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-rw-r--r--src/arch/alpha/tlb.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 69a33f32d..e61ae5c6d 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -44,7 +44,7 @@
#include "params/AlphaDTB.hh"
#include "params/AlphaITB.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
@@ -52,7 +52,7 @@ namespace AlphaISA
{
class TlbEntry;
- class TLB : public SimObject
+ class TLB : public BaseTLB
{
protected:
typedef std::multimap<Addr, int> PageTable;
@@ -79,6 +79,12 @@ namespace AlphaISA
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ assert(asn < (1 << 8));
+ flushAddr(vaddr, asn);
+ }
+
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1