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-rw-r--r--src/arch/alpha/tlb.hh158
1 files changed, 82 insertions, 76 deletions
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 955460649..ea5ba5539 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -36,6 +36,7 @@
#include "arch/alpha/ev5.hh"
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/pagetable.hh"
#include "arch/alpha/utility.hh"
#include "arch/alpha/vtophys.hh"
#include "base/statistics.hh"
@@ -45,82 +46,87 @@
class ThreadContext;
-class AlphaTLB : public SimObject
+namespace AlphaISA
{
- protected:
- typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
-
- AlphaISA::PTE *table; // the Page Table
- int size; // TLB Size
- int nlu; // not last used entry (for replacement)
-
- void nextnlu() { if (++nlu >= size) nlu = 0; }
- AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
-
- public:
- AlphaTLB(const std::string &name, int size);
- virtual ~AlphaTLB();
-
- int getsize() const { return size; }
-
- AlphaISA::PTE &index(bool advance = true);
- void insert(Addr vaddr, AlphaISA::PTE &pte);
-
- void flushAll();
- void flushProcesses();
- void flushAddr(Addr addr, uint8_t asn);
-
- // static helper functions... really EV5 VM traits
- static bool validVirtualAddress(Addr vaddr) {
- // unimplemented bits must be all 0 or all 1
- Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
- return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
- }
-
- static Fault checkCacheability(RequestPtr &req);
-
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
-};
-
-class AlphaITB : public AlphaTLB
-{
- protected:
- mutable Stats::Scalar<> hits;
- mutable Stats::Scalar<> misses;
- mutable Stats::Scalar<> acv;
- mutable Stats::Formula accesses;
-
- public:
- AlphaITB(const std::string &name, int size);
- virtual void regStats();
-
- Fault translate(RequestPtr &req, ThreadContext *tc) const;
-};
-
-class AlphaDTB : public AlphaTLB
-{
- protected:
- mutable Stats::Scalar<> read_hits;
- mutable Stats::Scalar<> read_misses;
- mutable Stats::Scalar<> read_acv;
- mutable Stats::Scalar<> read_accesses;
- mutable Stats::Scalar<> write_hits;
- mutable Stats::Scalar<> write_misses;
- mutable Stats::Scalar<> write_acv;
- mutable Stats::Scalar<> write_accesses;
- Stats::Formula hits;
- Stats::Formula misses;
- Stats::Formula acv;
- Stats::Formula accesses;
-
- public:
- AlphaDTB(const std::string &name, int size);
- virtual void regStats();
-
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
-};
+ class PTE;
+
+ class TLB : public SimObject
+ {
+ protected:
+ typedef std::multimap<Addr, int> PageTable;
+ PageTable lookupTable; // Quick lookup into page table
+
+ PTE *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
+
+ void nextnlu() { if (++nlu >= size) nlu = 0; }
+ PTE *lookup(Addr vpn, uint8_t asn) const;
+
+ public:
+ TLB(const std::string &name, int size);
+ virtual ~TLB();
+
+ int getsize() const { return size; }
+
+ PTE &index(bool advance = true);
+ void insert(Addr vaddr, PTE &pte);
+
+ void flushAll();
+ void flushProcesses();
+ void flushAddr(Addr addr, uint8_t asn);
+
+ // static helper functions... really EV5 VM traits
+ static bool validVirtualAddress(Addr vaddr) {
+ // unimplemented bits must be all 0 or all 1
+ Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
+ return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
+ }
+
+ static Fault checkCacheability(RequestPtr &req);
+
+ // Checkpointing
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+ };
+
+ class ITB : public TLB
+ {
+ protected:
+ mutable Stats::Scalar<> hits;
+ mutable Stats::Scalar<> misses;
+ mutable Stats::Scalar<> acv;
+ mutable Stats::Formula accesses;
+
+ public:
+ ITB(const std::string &name, int size);
+ virtual void regStats();
+
+ Fault translate(RequestPtr &req, ThreadContext *tc) const;
+ };
+
+ class DTB : public TLB
+ {
+ protected:
+ mutable Stats::Scalar<> read_hits;
+ mutable Stats::Scalar<> read_misses;
+ mutable Stats::Scalar<> read_acv;
+ mutable Stats::Scalar<> read_accesses;
+ mutable Stats::Scalar<> write_hits;
+ mutable Stats::Scalar<> write_misses;
+ mutable Stats::Scalar<> write_acv;
+ mutable Stats::Scalar<> write_accesses;
+ Stats::Formula hits;
+ Stats::Formula misses;
+ Stats::Formula acv;
+ Stats::Formula accesses;
+
+ public:
+ DTB(const std::string &name, int size);
+ virtual void regStats();
+
+ Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
+ };
+}
#endif // __ALPHA_MEMORY_HH__