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-rw-r--r--src/arch/alpha/isa.hh4
-rw-r--r--src/arch/alpha/kernel_stats.hh4
-rw-r--r--src/arch/alpha/pagetable.hh4
-rw-r--r--src/arch/alpha/process.hh2
-rw-r--r--src/arch/alpha/system.hh4
-rw-r--r--src/arch/alpha/tlb.hh4
6 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 6a88ee40b..6c06fc397 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -92,8 +92,8 @@ namespace AlphaISA
memset(ipr, 0, sizeof(ipr));
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
int
flattenIntIndex(int reg) const
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
index 188d3ec4b..06d20e6fa 100644
--- a/src/arch/alpha/kernel_stats.hh
+++ b/src/arch/alpha/kernel_stats.hh
@@ -86,8 +86,8 @@ class Statistics : public ::Kernel::Statistics
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 0b6524043..dc13d3790 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -142,8 +142,8 @@ struct TlbEntry : public Serializable
return ppn << PageShift;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
};
} // namespace AlphaISA
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index 6701017e0..cd45871b1 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -42,7 +42,7 @@ class AlphaLiveProcess : public LiveProcess
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void loadState(CheckpointIn &cp) override;
void initState();
void argsInit(int intSize, int pageSize);
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 3f4a2367e..f8ca54506 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -60,8 +60,8 @@ class AlphaSystem : public System
/**
* Serialization stuff
*/
- void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serializeSymtab(CheckpointOut &cp) const override;
+ void unserializeSymtab(CheckpointIn &cp) override;
/** Override startup() to provide a path to call setupFuncEvents()
*/
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 73ffda1f6..a8bdf30e1 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -117,8 +117,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// Most recently used page table entries
TlbEntry *EntryCache[3];