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-rw-r--r--src/arch/alpha/isa_traits.hh2
-rw-r--r--src/arch/alpha/miscregfile.hh2
-rw-r--r--src/arch/alpha/predecoder.hh2
-rw-r--r--src/arch/alpha/types.hh2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index ab3af0a1d..aae8271ce 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -38,7 +38,7 @@ namespace LittleEndianGuest {}
#include "arch/alpha/max_inst_regs.hh"
#include "arch/alpha/types.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class StaticInstPtr;
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index b194e00bb..1a215b8e4 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -36,7 +36,7 @@
#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
class Checkpoint;
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index 5502342e1..d18bb2402 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -34,7 +34,7 @@
#include "arch/alpha/types.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index 7905114b8..d670784c4 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -32,7 +32,7 @@
#ifndef __ARCH_ALPHA_TYPES_HH__
#define __ARCH_ALPHA_TYPES_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
namespace AlphaISA {