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-rw-r--r--src/arch/alpha/AlphaSystem.py4
-rw-r--r--src/arch/alpha/SConscript41
-rw-r--r--src/arch/alpha/ev5.cc17
-rw-r--r--src/arch/alpha/faults.cc76
-rw-r--r--src/arch/alpha/faults.hh13
-rw-r--r--src/arch/alpha/isa/decoder.isa76
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/arch/alpha/isa_traits.hh1
-rw-r--r--src/arch/alpha/linux/system.cc3
-rw-r--r--src/arch/alpha/linux/system.hh2
-rw-r--r--src/arch/alpha/pagetable.hh1
-rw-r--r--src/arch/alpha/predecoder.hh7
-rw-r--r--src/arch/alpha/regredir.cc9
-rw-r--r--src/arch/alpha/remote_gdb.cc17
-rw-r--r--src/arch/alpha/system.cc2
-rw-r--r--src/arch/alpha/system.hh5
-rw-r--r--src/arch/alpha/tlb.cc3
-rw-r--r--src/arch/alpha/utility.cc14
-rw-r--r--src/arch/alpha/utility.hh3
20 files changed, 130 insertions, 168 deletions
diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index f6d9eb4c6..fcbe81edd 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -27,6 +27,7 @@
# Authors: Nathan Binkert
from m5.params import *
+from m5.proxy import *
from System import System
class AlphaSystem(System):
@@ -42,6 +43,9 @@ class LinuxAlphaSystem(AlphaSystem):
system_type = 34
system_rev = 1 << 10
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
+
class FreebsdAlphaSystem(AlphaSystem):
type = 'FreebsdAlphaSystem'
system_type = 34
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index e3701d2a4..7e683364a 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,40 +34,33 @@ Import('*')
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
+ Source('freebsd/system.cc')
+ Source('idle_event.cc')
+ Source('interrupts.cc')
Source('ipr.cc')
Source('isa.cc')
+ Source('kernel_stats.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
+ Source('osfpal.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('regredir.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
+ Source('tru64/process.cc')
+ Source('tru64/system.cc')
+ Source('tru64/tru64.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('AlphaInterrupts.py')
+ SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
- if env['FULL_SYSTEM']:
- SimObject('AlphaInterrupts.py')
- SimObject('AlphaSystem.py')
-
- Source('idle_event.cc')
- Source('interrupts.cc')
- Source('kernel_stats.cc')
- Source('osfpal.cc')
- Source('stacktrace.cc')
- Source('system.cc')
- Source('vtophys.cc')
-
- Source('freebsd/system.cc')
- Source('linux/system.cc')
- Source('tru64/system.cc')
-
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
-
- Source('tru64/tru64.cc')
- Source('tru64/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 6259f8fc2..4dcc58ffe 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -36,7 +36,6 @@
#include "arch/alpha/tlb.hh"
#include "base/cp_annotate.hh"
#include "base/debug.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
@@ -44,8 +43,6 @@
namespace AlphaISA {
-#if FULL_SYSTEM
-
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
@@ -76,8 +73,6 @@ zeroRegisters(CPU *cpu)
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
-#endif
-
////////////////////////////////////////////////////////////////////////
//
//
@@ -201,10 +196,8 @@ ISA::readIpr(int idx, ThreadContext *tc)
return retval;
}
-#ifdef DEBUG
// Cause the simulator to break when changing to the following IPL
int break_ipl = -1;
-#endif
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
@@ -260,10 +253,8 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
case IPR_PALtemp23:
// write entire quad w/ no side-effect
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(ipr[idx], val, tc);
-#endif
ipr[idx] = val;
break;
@@ -291,14 +282,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->swpipl(ipr[idx]);
-#endif
break;
case IPR_DTB_CM:
-#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::user, tc);
@@ -306,7 +294,6 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::kernel, tc);
}
-#endif
case IPR_ICM:
// only write two mode bits - processor mode
@@ -483,8 +470,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
} // namespace AlphaISA
-#if FULL_SYSTEM
-
using namespace AlphaISA;
Fault
@@ -534,5 +519,3 @@ SimpleThread::simPalCheck(int palFunc)
return true;
}
-
-#endif // FULL_SYSTEM
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index c66c6f8ab..e4a5c9223 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -35,11 +35,9 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
namespace AlphaISA {
@@ -107,12 +105,12 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
-#if FULL_SYSTEM
-
void
AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
countStat()++;
PCState pc = tc->pcState();
@@ -135,32 +133,36 @@ void
ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
panic("Arithmetic traps are unimplemented!");
}
void
DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // Set fault address and flags. Even though we're modeling an
- // EV5, we use the EV6 technique of not latching fault registers
- // on VPTE loads (instead of locking the registers until IPR_VA is
- // read, like the EV5). The EV6 approach is cleaner and seems to
- // work with EV5 PAL code, but not the other way around.
- if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
- // set VA register with faulting address
- tc->setMiscRegNoEffect(IPR_VA, vaddr);
-
- // set MM_STAT register flags
- MachInst machInst = inst->machInst;
- tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(machInst) & 0x3f) << 11) |
- ((Ra(machInst) & 0x1f) << 6) |
- (flags & 0x3f)));
-
- // set VA_FORM register with faulting formatted address
- tc->setMiscRegNoEffect(IPR_VA_FORM,
- tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ if (FullSystem) {
+ // Set fault address and flags. Even though we're modeling an
+ // EV5, we use the EV6 technique of not latching fault registers
+ // on VPTE loads (instead of locking the registers until IPR_VA is
+ // read, like the EV5). The EV6 approach is cleaner and seems to
+ // work with EV5 PAL code, but not the other way around.
+ if (!tc->misspeculating() &&
+ reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ // set VA register with faulting address
+ tc->setMiscRegNoEffect(IPR_VA, vaddr);
+
+ // set MM_STAT register flags
+ MachInst machInst = inst->machInst;
+ tc->setMiscRegNoEffect(IPR_MM_STAT,
+ (((Opcode(machInst) & 0x3f) << 11) |
+ ((Ra(machInst) & 0x1f) << 6) |
+ (flags & 0x3f)));
+
+ // set VA_FORM register with faulting formatted address
+ tc->setMiscRegNoEffect(IPR_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
@@ -169,20 +171,25 @@ DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void
ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (!tc->misspeculating()) {
- tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ if (FullSystem) {
+ if (!tc->misspeculating()) {
+ tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+ tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
}
-#else
-
void
ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
+ if (FullSystem) {
+ ItbFault::invoke(tc);
+ return;
+ }
+
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(pc, entry);
@@ -197,6 +204,11 @@ ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
void
NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
+ if (FullSystem) {
+ DtbFault::invoke(tc, inst);
+ return;
+ }
+
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
@@ -211,7 +223,5 @@ NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
}
-#endif
-
} // namespace AlphaISA
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 3da97ccb4..7eddd14eb 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -33,7 +33,6 @@
#define __ARCH_ALPHA_FAULTS_HH__
#include "arch/alpha/pagetable.hh"
-#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
@@ -49,10 +48,8 @@ class AlphaFault : public FaultBase
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
};
@@ -111,10 +108,8 @@ class ArithmeticFault : public AlphaFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class InterruptFault : public AlphaFault
@@ -147,10 +142,8 @@ class DtbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class NDtbMissFault : public DtbFault
@@ -167,10 +160,8 @@ class NDtbMissFault : public DtbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class PDtbMissFault : public DtbFault
@@ -247,10 +238,8 @@ class ItbFault : public AlphaFault
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class ItbPageFault : public ItbFault
@@ -265,10 +254,8 @@ class ItbPageFault : public ItbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class ItbAcvFault : public ItbFault
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 106290784..4bbf83cce 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
- // return EV5 for FULL_SYSTEM and EV6 otherwise
- 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+ // return EV5 for FullSystem and EV6 otherwise
+ 1: implver({{ Rc = FullSystem ? 1 : 2 }});
}
}
}
@@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
* the parser to understand that.
*/
uint64_t unused_var M5_VAR_USED = Rb;
- Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+ Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable);
// All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
- 0xe000: decode FULL_SYSTEM {
+ 0xe000: decode FullSystem {
0: FailUnimpl::rc_se();
default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
}
- 0xf000: decode FULL_SYSTEM {
+ 0xf000: decode FullSystem {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag;
@@ -821,43 +821,41 @@ decode OPCODE default Unknown::unknown() {
}
}
-#if FULL_SYSTEM
- 0x00: CallPal::call_pal({{
- if (!palValid ||
- (palPriv
- && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
- // invalid pal function code, or attempt to do privileged
- // PAL call in non-kernel mode
- fault = new UnimplementedOpcodeFault;
- } else {
- // check to see if simulator wants to do something special
- // on this PAL call (including maybe suppress it)
- bool dopal = xc->simPalCheck(palFunc);
-
- if (dopal) {
- xc->setMiscReg(IPR_EXC_ADDR, NPC);
- NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+ 0x00: decode FullSystem {
+ 0: decode PALFUNC {
+ format EmulatedCallPal {
+ 0x00: halt ({{
+ exitSimLoop("halt instruction encountered");
+ }}, IsNonSpeculative);
+ 0x83: callsys({{
+ xc->syscall(R0);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+ // Read uniq reg into ABI return value register (r0)
+ 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
+ // Write uniq reg with value from ABI arg register (r16)
+ 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
}
}
- }}, IsNonSpeculative);
-#else
- 0x00: decode PALFUNC {
- format EmulatedCallPal {
- 0x00: halt ({{
- exitSimLoop("halt instruction encountered");
- }}, IsNonSpeculative);
- 0x83: callsys({{
- xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
- // Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
- // Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
- }
+ default: CallPal::call_pal({{
+ if (!palValid ||
+ (palPriv
+ && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
+ // invalid pal function code, or attempt to do privileged
+ // PAL call in non-kernel mode
+ fault = new UnimplementedOpcodeFault;
+ } else {
+ // check to see if simulator wants to do something special
+ // on this PAL call (including maybe suppress it)
+ bool dopal = xc->simPalCheck(palFunc);
+
+ if (dopal) {
+ xc->setMiscReg(IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+ }
+ }
+ }}, IsNonSpeculative);
}
-#endif
-#if FULL_SYSTEM
0x1b: decode PALMODE {
0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD {
@@ -924,8 +922,6 @@ decode OPCODE default Unknown::unknown() {
}
}
-#endif
-
format BasicOperate {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e3a6b18ab..5821ebcc5 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -45,7 +45,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+ if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 796c5e38e..e87a184c3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -64,6 +64,7 @@ output decoder {{
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
using namespace AlphaISA;
}};
@@ -81,6 +82,7 @@ output exec {{
#include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 852de5554..97cb845bf 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -36,7 +36,6 @@ namespace LittleEndianGuest {}
#include "arch/alpha/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace AlphaISA {
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 19a2a6ac3..6f3cf6b32 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -49,7 +49,6 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Thread.hh"
-#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "mem/physical.hh"
@@ -176,7 +175,7 @@ LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
Addr addr = 0;
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
Tick cpuFreq = tc->getCpuPtr()->frequency();
- Tick intrFreq = platform->intrFrequency();
+ assert(intrFreq);
FSTranslatingPortProxy* vp;
vp = tc->getVirtProxy();
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index e2fda39a8..5436a27b2 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -134,6 +134,8 @@ class LinuxAlphaSystem : public AlphaSystem
virtual void initState();
void setDelayLoop(ThreadContext *tc);
+
+ const Params *params() const { return (const Params *)_params; }
};
#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 59df93bef..b9091d5b6 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -34,7 +34,6 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/utility.hh"
-#include "config/full_system.hh"
namespace AlphaISA {
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..a08cddaec 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -34,7 +34,7 @@
#include "arch/alpha/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
class ThreadContext;
@@ -83,9 +83,8 @@ class Predecoder
{
ext_inst = inst;
emiIsReady = true;
-#if FULL_SYSTEM
- ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
-#endif
+ if (FullSystem)
+ ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
}
bool
diff --git a/src/arch/alpha/regredir.cc b/src/arch/alpha/regredir.cc
index 991138f11..861ded4d1 100644
--- a/src/arch/alpha/regredir.cc
+++ b/src/arch/alpha/regredir.cc
@@ -31,22 +31,13 @@
*/
#include "arch/alpha/regredir.hh"
-#include "config/full_system.hh"
namespace AlphaISA {
-#if FULL_SYSTEM
const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
- /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
- /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
- /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
- /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
} // namespace AlphaISA
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index cd9c8910d..aa120686c 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -121,15 +121,12 @@
#include <string>
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/alpha/vtophys.hh"
-#endif
#include "arch/alpha/kgdb.h"
#include "arch/alpha/regredir.hh"
#include "arch/alpha/remote_gdb.hh"
#include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
@@ -142,6 +139,7 @@
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace AlphaISA;
@@ -158,9 +156,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if !FULL_SYSTEM
- panic("acc function needs to be rewritten for SE mode\n");
-#else
+ if (!FullSystem)
+ panic("acc function needs to be rewritten for SE mode\n");
+
Addr last_va;
va = TruncPage(va);
@@ -173,8 +171,8 @@ RemoteGDB::acc(Addr va, size_t len)
"%#x < K0SEG + size\n", va);
return true;
} else {
- DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n",
- va);
+ DPRINTF(GDBAcc, "acc: Mapping invalid %#x "
+ "> K0SEG + size\n", va);
return false;
}
}
@@ -202,7 +200,6 @@ RemoteGDB::acc(Addr va, size_t len)
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
return true;
-#endif
}
/*
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index c7a646893..656ab4d6f 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -45,7 +45,7 @@
using namespace AlphaISA;
AlphaSystem::AlphaSystem(Params *p)
- : System(p)
+ : System(p), intrFreq(0)
{
consoleSymtab = new SymbolTable;
palSymtab = new SymbolTable;
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 0c725c3dc..0e809cb94 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -85,6 +85,8 @@ class AlphaSystem : public System
#endif
protected:
+ Tick intrFreq;
+
const Params *params() const { return (const Params *)_params; }
/** Add a function-based event to PALcode. */
@@ -104,6 +106,9 @@ class AlphaSystem : public System
}
virtual Addr fixFuncEventAddr(Addr addr);
+
+ public:
+ void setIntrFreq(Tick freq) { intrFreq = freq; }
};
#endif // __ARCH_ALPHA_SYSTEM_HH__
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 26d290a50..f1199b9b6 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -42,6 +42,7 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
+#include "sim/full_system.hh"
using namespace std;
@@ -370,7 +371,7 @@ Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
- if (FULL_SYSTEM && PcPAL(req->getPC()))
+ if (FullSystem && PcPAL(req->getPC()))
req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) {
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 4de77ffd4..1bac650a0 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -30,18 +30,20 @@
*/
#include "arch/alpha/utility.hh"
-
-#if FULL_SYSTEM
#include "arch/alpha/vtophys.hh"
#include "mem/fs_translating_port_proxy.hh"
-#endif
+#include "sim/full_system.hh"
namespace AlphaISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
+ if (!FullSystem) {
+ panic("getArgument() is Full system only\n");
+ M5_DUMMY_RETURN;
+ }
+
const int NumArgumentRegs = 6;
if (number < NumArgumentRegs) {
if (fp)
@@ -55,10 +57,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
(number-NumArgumentRegs) * sizeof(uint64_t));
return arg;
}
-#else
- panic("getArgument() is Full system only\n");
- M5_DUMMY_RETURN;
-#endif
}
void
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index c0c985c34..a9b5c4cba 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -36,7 +36,6 @@
#include "arch/alpha/registers.hh"
#include "arch/alpha/types.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "arch/alpha/ev5.hh"
@@ -96,9 +95,7 @@ RoundPage(Addr addr)
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId);
-#endif
void copyRegs(ThreadContext *src, ThreadContext *dest);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 02:32:50 +0000