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-rw-r--r--src/arch/alpha/mmapped_ipr.hh4
-rw-r--r--src/arch/alpha/utility.hh3
2 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/alpha/mmapped_ipr.hh b/src/arch/alpha/mmapped_ipr.hh
index 6c3403b33..24f7ce335 100644
--- a/src/arch/alpha/mmapped_ipr.hh
+++ b/src/arch/alpha/mmapped_ipr.hh
@@ -44,14 +44,14 @@ class ThreadContext;
namespace AlphaISA {
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
panic("No handleIprRead implementation in Alpha\n");
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
panic("No handleIprWrite implementation in Alpha\n");
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a9b5c4cba..1cd19cc95 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -67,7 +67,8 @@ void zeroRegisters(TC *tc);
// Alpha IPR register accessors
inline bool PcPAL(Addr addr) { return addr & 0x3; }
-inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{ tc->activate(Cycles(0)); }
////////////////////////////////////////////////////////////////////////
//