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-rw-r--r--src/arch/alpha/SConscript11
-rw-r--r--src/arch/alpha/ev5.cc75
-rw-r--r--src/arch/alpha/faults.cc67
-rw-r--r--src/arch/alpha/faults.hh39
-rw-r--r--src/arch/alpha/isa_traits.hh9
-rw-r--r--src/arch/alpha/miscregfile.cc25
-rw-r--r--src/arch/alpha/miscregfile.hh7
-rw-r--r--src/arch/alpha/process.cc6
-rw-r--r--src/arch/alpha/regfile.cc2
-rw-r--r--src/arch/alpha/utility.hh4
10 files changed, 129 insertions, 116 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 4f293e22f..04bac3996 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -32,27 +32,28 @@
Import('*')
if env['TARGET_ISA'] == 'alpha':
+ Source('ev5.cc')
Source('faults.cc')
Source('floatregfile.cc')
Source('intregfile.cc')
+ Source('ipr.cc')
Source('miscregfile.cc')
+ Source('pagetable.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
+ Source('tlb.cc')
Source('utility.cc')
+ SimObject('AlphaTLB.py')
+
if env['FULL_SYSTEM']:
SimObject('AlphaSystem.py')
- SimObject('AlphaTLB.py')
- Source('ev5.cc')
Source('idle_event.cc')
- Source('ipr.cc')
Source('kernel_stats.cc')
Source('osfpal.cc')
- Source('pagetable.cc')
Source('stacktrace.cc')
Source('system.cc')
- Source('tlb.cc')
Source('vtophys.cc')
Source('freebsd/system.cc')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 86b8fd2d0..123506e40 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -68,22 +68,6 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
delete reset;
}
-////////////////////////////////////////////////////////////////////////
-//
-//
-//
-void
-AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
-{
- for (int i = 0; i < NumInternalProcRegs; ++i) {
- tc->setMiscRegNoEffect(i, 0);
- }
-
- tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
- tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
- tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
-}
-
template <class CPU>
void
@@ -171,6 +155,24 @@ AlphaISA::MiscRegFile::getDataAsid()
return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
+#endif
+
+////////////////////////////////////////////////////////////////////////
+//
+//
+//
+void
+AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
+{
+ for (int i = 0; i < NumInternalProcRegs; ++i) {
+ tc->setMiscRegNoEffect(i, 0);
+ }
+
+ tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
+ tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
+ tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
+}
+
AlphaISA::MiscReg
AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
@@ -340,8 +342,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
+#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(old, val, tc);
+#endif
break;
case AlphaISA::IPR_DTB_PTE:
@@ -368,11 +372,14 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
+#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->swpipl(ipr[idx]);
+#endif
break;
case AlphaISA::IPR_DTB_CM:
+#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
@@ -380,6 +387,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
if (tc->getKernelStats())
tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
}
+#endif
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
@@ -468,27 +476,27 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getDTBPtr()->flushAddr(val,
- DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
struct AlphaISA::PTE pte;
// FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
+ if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
- pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
+ pte.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
+ pte.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getDTBPtr()->insert(val, pte);
@@ -499,20 +507,20 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
struct AlphaISA::PTE pte;
// FIXME: granularity hints NYI...
- if (ITB_PTE_GH(val) != 0)
+ if (EV5::ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- pte.ppn = ITB_PTE_PPN(val);
- pte.xre = ITB_PTE_XRE(val);
+ pte.ppn = EV5::ITB_PTE_PPN(val);
+ pte.xre = EV5::ITB_PTE_XRE(val);
pte.xwe = 0;
- pte.fonr = ITB_PTE_FONR(val);
- pte.fonw = ITB_PTE_FONW(val);
- pte.asma = ITB_PTE_ASMA(val);
- pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
+ pte.fonr = EV5::ITB_PTE_FONR(val);
+ pte.fonw = EV5::ITB_PTE_FONW(val);
+ pte.asma = EV5::ITB_PTE_ASMA(val);
+ pte.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
@@ -538,7 +546,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getITBPtr()->flushAddr(val,
- ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+ EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
@@ -558,6 +566,7 @@ AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
}
}
+#if FULL_SYSTEM
/**
* Check for special simulator handling of specific PAL calls.
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 149729351..d81b55b33 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -29,13 +29,13 @@
* Kevin Lim
*/
+#include "arch/alpha/ev5.hh"
#include "arch/alpha/faults.hh"
+#include "arch/alpha/tlb.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
-#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
-#else
+#if !FULL_SYSTEM
#include "sim/process.hh"
#include "mem/page_table.hh"
#endif
@@ -83,10 +83,6 @@ FaultName DtbAlignmentFault::_name = "unalign";
FaultVect DtbAlignmentFault::_vect = 0x0301;
FaultStat DtbAlignmentFault::_count;
-FaultName ItbMissFault::_name = "itbmiss";
-FaultVect ItbMissFault::_vect = 0x0181;
-FaultStat ItbMissFault::_count;
-
FaultName ItbPageFault::_name = "itbmiss";
FaultVect ItbPageFault::_vect = 0x0181;
FaultStat ItbPageFault::_count;
@@ -176,6 +172,63 @@ void ItbFault::invoke(ThreadContext * tc)
AlphaFault::invoke(tc);
}
+#else
+
+void ItbPageFault::invoke(ThreadContext * tc)
+{
+ Process *p = tc->getProcessPtr();
+ Addr physaddr;
+ bool success = p->pTable->translate(pc, physaddr);
+ if(!success) {
+ panic("Tried to execute unmapped address %#x.\n", pc);
+ } else {
+ VAddr vaddr(pc);
+ VAddr paddr(physaddr);
+
+ PTE pte;
+ pte.tag = vaddr.vpn();
+ pte.ppn = paddr.vpn();
+ pte.xre = 15; //This can be read in all modes.
+ pte.xwe = 1; //This can be written only in kernel mode.
+ pte.asn = p->M5_pid; //Address space number.
+ pte.asma = false; //Only match on this ASN.
+ pte.fonr = false; //Don't fault on read.
+ pte.fonw = false; //Don't fault on write.
+ pte.valid = true; //This entry is valid.
+
+ tc->getITBPtr()->insert(vaddr.page(), pte);
+ }
+}
+
+void NDtbMissFault::invoke(ThreadContext * tc)
+{
+ Process *p = tc->getProcessPtr();
+ Addr physaddr;
+ bool success = p->pTable->translate(vaddr, physaddr);
+ if(!success) {
+ p->checkAndAllocNextPage(vaddr);
+ success = p->pTable->translate(vaddr, physaddr);
+ }
+ if(!success) {
+ panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+ } else {
+ VAddr paddr(physaddr);
+
+ PTE pte;
+ pte.tag = vaddr.vpn();
+ pte.ppn = paddr.vpn();
+ pte.xre = 15; //This can be read in all modes.
+ pte.xwe = 15; //This can be written in all modes.
+ pte.asn = p->M5_pid; //Address space number.
+ pte.asma = false; //Only match on this ASN.
+ pte.fonr = false; //Don't fault on read.
+ pte.fonw = false; //Don't fault on write.
+ pte.valid = true; //This entry is valid.
+
+ tc->getDTBPtr()->insert(vaddr.page(), pte);
+ }
+}
+
#endif
} // namespace AlphaISA
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index ed0c3a6b1..49ba25966 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -35,9 +35,7 @@
#include "config/full_system.hh"
#include "sim/faults.hh"
-#if FULL_SYSTEM
#include "arch/alpha/pagetable.hh"
-#endif
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -140,8 +138,7 @@ class InterruptFault : public AlphaFault
class DtbFault : public AlphaFault
{
-#if FULL_SYSTEM
- private:
+ protected:
AlphaISA::VAddr vaddr;
uint32_t reqFlags;
uint64_t flags;
@@ -149,7 +146,6 @@ class DtbFault : public AlphaFault
DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
{ }
-#endif
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
@@ -165,14 +161,15 @@ class NDtbMissFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
-#if FULL_SYSTEM
NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
-#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
+#if !FULL_SYSTEM
+ void invoke(ThreadContext * tc);
+#endif
};
class PDtbMissFault : public DtbFault
@@ -182,11 +179,9 @@ class PDtbMissFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
-#if FULL_SYSTEM
PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
-#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -199,11 +194,9 @@ class DtbPageFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
-#if FULL_SYSTEM
DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
-#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -216,11 +209,9 @@ class DtbAcvFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
-#if FULL_SYSTEM
DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
-#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -233,11 +224,9 @@ class DtbAlignmentFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
-#if FULL_SYSTEM
DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
-#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -245,7 +234,7 @@ class DtbAlignmentFault : public DtbFault
class ItbFault : public AlphaFault
{
- private:
+ protected:
Addr pc;
public:
ItbFault(Addr _pc)
@@ -259,21 +248,6 @@ class ItbFault : public AlphaFault
#endif
};
-class ItbMissFault : public ItbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
- public:
- ItbMissFault(Addr pc)
- : ItbFault(pc)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
class ItbPageFault : public ItbFault
{
private:
@@ -287,6 +261,9 @@ class ItbPageFault : public ItbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
+#if !FULL_SYSTEM
+ void invoke(ThreadContext * tc);
+#endif
};
class ItbAcvFault : public ItbFault
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 7dc7e5151..53eea5f69 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -63,14 +63,13 @@ namespace AlphaISA
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
-#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Translation stuff
//
- const Addr PteShift = 3;
+ const Addr PteShift = 3;
const Addr NPtePageShift = PageShift - PteShift;
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;
@@ -90,6 +89,8 @@ namespace AlphaISA
// For loading... XXX This maybe could be USegEnd?? --ali
const Addr LoadAddrMask = ULL(0xffffffffff);
+#if FULL_SYSTEM
+
////////////////////////////////////////////////////////////////////////
//
// Interrupt levels
@@ -114,6 +115,8 @@ namespace AlphaISA
NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
};
+#endif
+
// EV5 modes
enum mode_type
{
@@ -124,8 +127,6 @@ namespace AlphaISA
mode_number // number of modes
};
-#endif
-
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 1af97adcf..cb5875349 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -43,9 +43,7 @@ namespace AlphaISA
SERIALIZE_SCALAR(uniq);
SERIALIZE_SCALAR(lock_flag);
SERIALIZE_SCALAR(lock_addr);
-#if FULL_SYSTEM
SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-#endif
}
void
@@ -55,9 +53,7 @@ namespace AlphaISA
UNSERIALIZE_SCALAR(uniq);
UNSERIALIZE_SCALAR(lock_flag);
UNSERIALIZE_SCALAR(lock_addr);
-#if FULL_SYSTEM
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-#endif
}
MiscReg
@@ -74,15 +70,9 @@ namespace AlphaISA
return lock_addr;
case MISCREG_INTR:
return intr_flag;
-#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
return ipr[misc_reg];
-#else
- default:
- panic("Attempt to read an invalid misc register!");
- return 0;
-#endif
}
}
@@ -100,14 +90,8 @@ namespace AlphaISA
return lock_addr;
case MISCREG_INTR:
return intr_flag;
-#if FULL_SYSTEM
default:
return readIpr(misc_reg, tc);
-#else
- default:
- panic("No faulting misc regs in SE mode!");
- return 0;
-#endif
}
}
@@ -130,15 +114,10 @@ namespace AlphaISA
case MISCREG_INTR:
intr_flag = val;
return;
-#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
ipr[misc_reg] = val;
return;
-#else
- default:
- panic("Attempt to write to an invalid misc register!");
-#endif
}
}
@@ -163,11 +142,7 @@ namespace AlphaISA
intr_flag = val;
return;
default:
-#if FULL_SYSTEM
setIpr(misc_reg, val, tc);
-#else
- panic("No registers with side effects in SE mode!");
-#endif
return;
}
}
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index aea702849..022b6404a 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -34,7 +34,6 @@
#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
-#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
@@ -70,9 +69,7 @@ namespace AlphaISA
public:
MiscRegFile()
{
-#if FULL_SYSTEM
initializeIprTable();
-#endif
}
MiscReg readRegNoEffect(int misc_reg);
@@ -100,7 +97,6 @@ namespace AlphaISA
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
-#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
@@ -110,13 +106,10 @@ namespace AlphaISA
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-#endif
friend class RegFile;
};
-#if FULL_SYSTEM
void copyIprs(ThreadContext *src, ThreadContext *dest);
-#endif
}
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 85619e493..a9848ebb5 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -71,6 +71,12 @@ AlphaLiveProcess::startup()
argsInit(MachineBytes, VMPageSize);
threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
+ //Opperate in user mode
+ threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18);
+ //No super page mapping
+ threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0);
+ //Set this to 0 for now, but it should be unique for each process
+ threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
}
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 3b42ca9bc..2653310d7 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -94,8 +94,6 @@ namespace AlphaISA
dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
-#if FULL_SYSTEM
copyIprs(src, dest);
-#endif
}
}
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 5d461a0f9..11357bc44 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -115,7 +115,6 @@ namespace AlphaISA
inline void startupCPU(ThreadContext *tc, int cpuId) {
tc->activate(0);
}
-#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
@@ -142,8 +141,9 @@ namespace AlphaISA
RoundPage(Addr addr)
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
- void initCPU(ThreadContext *tc, int cpuId);
void initIPRs(ThreadContext *tc, int cpuId);
+#if FULL_SYSTEM
+ void initCPU(ThreadContext *tc, int cpuId);
/**
* Function to check for and process any interrupts.
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 16:58:46 +0000