diff options
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/isa.hh | 12 | ||||
| -rw-r--r-- | src/arch/alpha/registers.hh | 10 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index 80d8ab149..36e708450 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -110,6 +110,18 @@ namespace AlphaISA return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 03bbd8aaf..151ea7d7c 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -34,6 +34,7 @@ #include "arch/alpha/generated/max_inst_regs.hh" #include "arch/alpha/ipr.hh" #include "arch/generic/types.hh" +#include "arch/generic/vec_reg.hh" #include "base/types.hh" namespace AlphaISA { @@ -56,6 +57,15 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + union AnyReg { IntReg intreg; |