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-rw-r--r--src/arch/alpha/tlb.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index bcf61f3bf..a740da388 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -225,7 +225,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
"IPR memory space not implemented!");
} else {
// mark request as uncacheable
- req->setFlags(Request::UNCACHEABLE);
+ req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
// Clear bits 42:35 of the physical address (10-2 in
// Tsunami manual)