4 files changed, 36 insertions, 26 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 1e8231b66..4d72104b1 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -43,6 +43,24 @@
 
 namespace AlphaISA {
 
+template<typename T>
+TLB *
+getITBPtr(T *tc)
+{
+    auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
+    assert(tlb);
+    return tlb;
+}
+
+template<typename T>
+TLB *
+getDTBPtr(T *tc)
+{
+    auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
+    assert(tlb);
+    return tlb;
+}
+
 ////////////////////////////////////////////////////////////////////////
 //
 //  Machine dependent functions
@@ -161,7 +179,7 @@ ISA::readIpr(int idx, ThreadContext *tc)
 
       case IPR_DTB_PTE:
         {
-            TlbEntry &entry = tc->getDTBPtr()->index(1);
+            TlbEntry &entry = getDTBPtr(tc)->index(1);
 
             retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
@@ -358,21 +376,21 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
         // really a control write
         ipr[idx] = 0;
 
-        tc->getDTBPtr()->flushAll();
+        getDTBPtr(tc)->flushAll();
         break;
 
       case IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        tc->getDTBPtr()->flushProcesses();
+        getDTBPtr(tc)->flushProcesses();
         break;
 
       case IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
+        getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
         break;
 
       case IPR_DTB_TAG: {
@@ -395,7 +413,7 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
           entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          tc->getDTBPtr()->insert(val, entry);
+          getDTBPtr(tc)->insert(val, entry);
       }
         break;
 
@@ -419,7 +437,7 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
           entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
+          getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry);
       }
         break;
 
@@ -427,21 +445,21 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
         // really a control write
         ipr[idx] = 0;
 
-        tc->getITBPtr()->flushAll();
+        getITBPtr(tc)->flushAll();
         break;
 
       case IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        tc->getITBPtr()->flushProcesses();
+        getITBPtr(tc)->flushProcesses();
         break;
 
       case IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
+        getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
         break;
 
       default:
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 59d95000b..4a829cd9b 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -202,7 +202,7 @@ ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         panic("Tried to execute unmapped address %#x.\n", pc);
     } else {
         VAddr vaddr(pc);
-        tc->getITBPtr()->insert(vaddr.page(), entry);
+        dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
     }
 }
 
@@ -224,7 +224,7 @@ NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
     if (!success) {
         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
     } else {
-        tc->getDTBPtr()->insert(vaddr.page(), entry);
+        dynamic_cast<TLB *>(tc->getDTBPtr())->insert(vaddr.page(), entry);
     }
 }
 
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index fcd2b518b..f77c45854 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -616,13 +616,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
-{
-    panic("Not implemented\n");
-    return NoFault;
-}
-
-Fault
 TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 {
     return NoFault;
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index b9b6228e2..08166bc6e 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -141,14 +141,13 @@ class TLB : public BaseTLB
     Fault translateInst(RequestPtr req, ThreadContext *tc);
 
   public:
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-                         Translation *translation, Mode mode);
-    /**
-     * translateFunctional stub function for future CheckerCPU support
-     */
-    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
-    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+    Fault translateAtomic(
+            RequestPtr req, ThreadContext *tc, Mode mode) override;
+    void translateTiming(
+            RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode) override;
+    Fault finalizePhysical(
+            RequestPtr req, ThreadContext *tc, Mode mode) const override;
 };
 
 } // namespace AlphaISA