4 files changed, 10 insertions, 7 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 106290784..eecf695da 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
             0x6c: decode RA {
                 31: decode IMM {
                     1: decode INTIMM {
-                        // return EV5 for FULL_SYSTEM and EV6 otherwise
-                        1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+                        // return EV5 for FullSystem and EV6 otherwise
+                        1: implver({{ Rc = FullSystem ? 1 : 2 }});
                     }
                 }
             }
@@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
                  * the parser to understand that.
                  */
                 uint64_t unused_var M5_VAR_USED = Rb;
-                Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+                Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
             }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
         }
 
-        0xe000: decode FULL_SYSTEM {
+        0xe000: decode FullSystem {
             0: FailUnimpl::rc_se();
             default: BasicOperate::rc({{
                 Ra = IntrFlag;
                 IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
         }
-        0xf000: decode FULL_SYSTEM {
+        0xf000: decode FullSystem {
             0: FailUnimpl::rs_se();
             default: BasicOperate::rs({{
                 Ra = IntrFlag;
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e3a6b18ab..5821ebcc5 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -45,7 +45,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;  // dummy... this ipr access should not fault
-        if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+        if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 796c5e38e..e87a184c3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -64,6 +64,7 @@ output decoder {{
 #include "config/ss_compatible_fp.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
+#include "sim/full_system.hh"
 
 using namespace AlphaISA;
 }};
@@ -81,6 +82,7 @@ output exec {{
 #include "cpu/exetrace.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/full_system.hh"
 #include "sim/pseudo_inst.hh"
 #include "sim/sim_exit.hh"
 
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index b211c4923..623eafb8a 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -42,6 +42,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/TLB.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -370,7 +371,7 @@ Fault
 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
-    if (FULL_SYSTEM && PcPAL(req->getPC()))
+    if (FullSystem && PcPAL(req->getPC()))
         req->setFlags(Request::PHYSICAL);
 
     if (PcPAL(req->getPC())) {