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-rw-r--r--src/arch/alpha/SConscript2
-rw-r--r--src/arch/alpha/isa/branch.isa7
-rw-r--r--src/arch/alpha/isa/fp.isa4
-rw-r--r--src/arch/alpha/isa/int.isa6
-rw-r--r--src/arch/alpha/isa/main.isa5
-rw-r--r--src/arch/alpha/isa/mem.isa94
-rw-r--r--src/arch/alpha/isa/pal.isa7
-rw-r--r--src/arch/alpha/isa_traits.hh2
-rw-r--r--src/arch/alpha/regfile.hh11
-rw-r--r--src/arch/alpha/remote_gdb.cc12
-rw-r--r--src/arch/alpha/syscallreturn.hh45
-rw-r--r--src/arch/alpha/system.cc6
-rw-r--r--src/arch/alpha/system.hh2
-rw-r--r--src/arch/alpha/utility.hh4
14 files changed, 73 insertions, 134 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 3cc5ec270..addd49884 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -52,6 +52,7 @@ base_sources = Split('''
intregfile.cc
miscregfile.cc
regfile.cc
+ remote_gdb.cc
''')
# Full-system sources
@@ -66,7 +67,6 @@ full_system_sources = Split('''
osfpal.cc
pagetable.cc
stacktrace.cc
- remote_gdb.cc
system.cc
tlb.cc
tru64/system.cc
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index 7438e7e18..974193efd 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -218,7 +218,7 @@ def template JumpOrBranchDecode {{
def format CondBranch(code) {{
code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
- iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
+ iop = InstObjParams(name, Name, 'Branch', code,
('IsDirectControl', 'IsCondControl'))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -230,8 +230,7 @@ let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Declare basic control transfer w/o link (i.e. link reg is R31)
nolink_code = 'NPC = %s;\n' % npc_expr
- nolink_iop = InstObjParams(name, Name, base_class,
- CodeBlock(nolink_code), flags)
+ nolink_iop = InstObjParams(name, Name, base_class, nolink_code, flags)
header_output = BasicDeclare.subst(nolink_iop)
decoder_output = BasicConstructor.subst(nolink_iop)
exec_output = BasicExecute.subst(nolink_iop)
@@ -239,7 +238,7 @@ def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Generate declaration of '*AndLink' version, append to decls
link_code = 'Ra = NPC & ~3;\n' + nolink_code
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
- CodeBlock(link_code), flags)
+ link_code, flags)
header_output += BasicDeclare.subst(link_iop)
decoder_output += BasicConstructor.subst(link_iop)
exec_output += BasicExecute.subst(link_iop)
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 3b5575f62..c845ea442 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -293,7 +293,7 @@ def template FloatingPointDecode {{
// currently unimplemented (will fail).
// - Generates NOP if FC == 31.
def format FloatingPointOperate(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+ iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -303,7 +303,7 @@ def format FloatingPointOperate(code, *opt_args) {{
// Special format for cvttq where rounding mode is pre-decoded
def format FPFixedRounding(code, class_suffix, *opt_args) {{
Name += class_suffix
- iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
+ iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
decode_block = FloatingPointDecode.subst(iop)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa
index 45e096ebd..bd9c3ccd9 100644
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -113,16 +113,14 @@ def format IntegerOperate(code, *opt_flags) {{
imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
# generate declaration for register version
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BasicExecute.subst(iop)
if uses_imm:
# append declaration for imm version
- imm_cblk = CodeBlock(imm_code)
- imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
+ imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_code,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 6e65cf9d3..d72dfe34a 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -338,7 +338,7 @@ def template BasicDecodeWithMnemonic {{
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
- iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -424,8 +424,7 @@ def template OperateNopCheckDecode {{
// Like BasicOperate format, but generates NOP if RC/FC == 31
def format BasicOperateWithNopCheck(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
- opt_args)
+ iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = OperateNopCheckDecode.subst(iop)
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 02291ed6b..c0bdd2c05 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -126,7 +126,7 @@ output decoder {{
}};
def format LoadAddress(code) {{
- iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
+ iop = InstObjParams(name, Name, 'MemoryDisp32', code)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -191,22 +191,28 @@ def template CompleteAccDeclare {{
}};
-def template LoadStoreConstructor {{
+def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
- %(ea_constructor)s;
+ %(constructor)s;
}
+}};
+
+def template MemAccConstructor {{
inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
- %(memacc_constructor)s;
+ %(constructor)s;
}
+}};
+
+def template LoadStoreConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
@@ -227,7 +233,7 @@ def template EACompExecute {{
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
- %(code)s;
+ %(ea_code)s;
if (fault == NoFault) {
%(op_wb)s;
@@ -253,7 +259,7 @@ def template LoadMemAccExecute {{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- %(code)s;
+ %(memacc_code)s;
}
if (fault == NoFault) {
@@ -352,7 +358,7 @@ def template StoreMemAccExecute {{
EA = xc->getEA();
if (fault == NoFault) {
- %(code)s;
+ %(memacc_code)s;
}
if (fault == NoFault) {
@@ -497,7 +503,7 @@ def template MiscMemAccExecute {{
EA = xc->getEA();
if (fault == NoFault) {
- %(code)s;
+ %(memacc_code)s;
}
return NoFault;
@@ -582,63 +588,24 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
- # generate code block objects
- ea_cblk = CodeBlock(ea_code)
- memacc_cblk = CodeBlock(memacc_code)
- postacc_cblk = CodeBlock(postacc_code)
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
- # generate InstObjParams for EAComp object
- ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
-
- # generate InstObjParams for MemAcc object
- memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
- # in the split execution model, the MemAcc portion is responsible
- # for the post-access code.
- memacc_iop.postacc_code = postacc_cblk.code
-
- # generate InstObjParams for InitiateAcc, CompleteAcc object
- # The code used depends on the template being used
- if (exec_template_base == 'Load'):
- initiateacc_cblk = CodeBlock(ea_code + memacc_code)
- completeacc_cblk = CodeBlock(memacc_code + postacc_code)
- elif (exec_template_base.startswith('Store')):
- initiateacc_cblk = CodeBlock(ea_code + memacc_code)
- completeacc_cblk = CodeBlock(postacc_code)
- else:
- initiateacc_cblk = ''
- completeacc_cblk = ''
-
- initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
- inst_flags)
-
- completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
- inst_flags)
-
- if (exec_template_base == 'Load'):
- initiateacc_iop.ea_code = ea_cblk.code
- initiateacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.postacc_code = postacc_cblk.code
- elif (exec_template_base.startswith('Store')):
- initiateacc_iop.ea_code = ea_cblk.code
- initiateacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.postacc_code = postacc_cblk.code
-
- # generate InstObjParams for unified execution
- cblk = CodeBlock(ea_code + memacc_code + postacc_code)
- iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
-
- iop.ea_constructor = ea_cblk.constructor
- iop.ea_code = ea_cblk.code
- iop.memacc_constructor = memacc_cblk.constructor
- iop.memacc_code = memacc_cblk.code
- iop.postacc_code = postacc_cblk.code
+ # Generate InstObjParams for each of the three objects. Note that
+ # they differ only in the set of code objects contained (which in
+ # turn affects the object's overall operand list).
+ iop = InstObjParams(name, Name, base_class,
+ { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+ inst_flags)
+ ea_iop = InstObjParams(name, Name, base_class,
+ { 'ea_code':ea_code },
+ inst_flags)
+ memacc_iop = InstObjParams(name, Name, base_class,
+ { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+ inst_flags)
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
@@ -659,13 +626,16 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
# (header_output, decoder_output, decode_block, exec_output)
- return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
+ return (LoadStoreDeclare.subst(iop),
+ EACompConstructor.subst(ea_iop)
+ + MemAccConstructor.subst(memacc_iop)
+ + LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
EACompExecute.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
- + initiateAccTemplate.subst(initiateacc_iop)
- + completeAccTemplate.subst(completeacc_iop))
+ + initiateAccTemplate.subst(iop)
+ + completeAccTemplate.subst(iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index f4c10da1d..294b92e2f 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -68,7 +68,7 @@ output decoder {{
}};
def format EmulatedCallPal(code, *flags) {{
- iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'EmulatedCallPal', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -131,7 +131,7 @@ output decoder {{
}};
def format CallPal(code, *flags) {{
- iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'CallPalBase', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -269,8 +269,7 @@ output decoder {{
def format HwMoveIPR(code, *flags) {{
all_flags = ['IprAccessOp']
all_flags += flags
- iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
- all_flags)
+ iop = InstObjParams(name, Name, 'HwMoveIPR', code, all_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 35d9ce843..a267ac034 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -132,7 +132,7 @@ namespace AlphaISA
const int NumPALShadowRegs = 8;
const int NumFloatArchRegs = 32;
// @todo: Figure out what this number really should be.
- const int NumMiscArchRegs = 32;
+ const int NumMiscArchRegs = 77;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index ff5830822..54372da36 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -78,13 +78,11 @@ namespace AlphaISA
Addr readNextNPC()
{
- return nnpc;
+ return npc + sizeof(MachInst);
}
void setNextNPC(Addr val)
- {
- nnpc = val;
- }
+ { }
protected:
IntRegFile intRegFile; // (signed) integer register file
@@ -189,6 +187,11 @@ namespace AlphaISA
}
};
+ static inline int flattenIntIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index f23fc3205..4637bd7a6 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -121,14 +121,18 @@
#include <string>
#include <unistd.h>
+#include "config/full_system.hh"
+#if FULL_SYSTEM
+#include "arch/alpha/vtophys.hh"
+#endif
+
#include "arch/alpha/kgdb.h"
+#include "arch/alpha/utility.hh"
#include "arch/alpha/remote_gdb.hh"
-#include "arch/vtophys.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "mem/physical.hh"
@@ -152,6 +156,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
bool
RemoteGDB::acc(Addr va, size_t len)
{
+#if !FULL_SYSTEM
+ panic("acc function needs to be rewritten for SE mode\n");
+#else
Addr last_va;
va = TheISA::TruncPage(va);
@@ -191,6 +198,7 @@ RemoteGDB::acc(Addr va, size_t len)
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
return true;
+#endif
}
///////////////////////////////////////////////////////////
diff --git a/src/arch/alpha/syscallreturn.hh b/src/arch/alpha/syscallreturn.hh
index 803c3b7da..47b4ac8c7 100644
--- a/src/arch/alpha/syscallreturn.hh
+++ b/src/arch/alpha/syscallreturn.hh
@@ -32,54 +32,25 @@
#ifndef __ARCH_ALPHA_SYSCALLRETURN_HH__
#define __ARCH_ALPHA_SYSCALLRETURN_HH__
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint64_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint64_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
+#include "cpu/thread_context.hh"
+#include "sim/syscallreturn.hh"
namespace AlphaISA
{
- static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+ static inline void setSyscallReturn(SyscallReturn return_value,
+ ThreadContext * tc)
{
// check for error condition. Alpha syscall convention is to
// indicate success/failure in reg a3 (r19) and put the
// return value itself in the standard return value reg (v0).
if (return_value.successful()) {
// no error
- regs->setIntReg(SyscallSuccessReg, 0);
- regs->setIntReg(ReturnValueReg, return_value.value());
+ tc->setIntReg(SyscallSuccessReg, 0);
+ tc->setIntReg(ReturnValueReg, return_value.value());
} else {
// got an error, return details
- regs->setIntReg(SyscallSuccessReg, (IntReg)-1);
- regs->setIntReg(ReturnValueReg, -return_value.value());
+ tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
+ tc->setIntReg(ReturnValueReg, -return_value.value());
}
}
}
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index cd923948c..ed0938aeb 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -195,12 +195,6 @@ AlphaSystem::setAlphaAccess(Addr access)
panic("could not find m5AlphaAccess\n");
}
-bool
-AlphaSystem::breakpoint()
-{
- return remoteGDB[0]->trap(SIGTRAP);
-}
-
void
AlphaSystem::serialize(std::ostream &os)
{
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 0c073a68c..f92b71c9a 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -56,8 +56,6 @@ class AlphaSystem : public System
~AlphaSystem();
- virtual bool breakpoint();
-
/**
* Serialization stuff
*/
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 100736555..9a06cc2a4 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -121,9 +121,9 @@ namespace AlphaISA
template <class TC>
void zeroRegisters(TC *tc);
-#if FULL_SYSTEM
// Alpha IPR register accessors
- inline bool PcPAL(Addr addr) { return addr & 0x1; }
+ inline bool PcPAL(Addr addr) { return addr & 0x3; }
+#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 18:17:29 +0000