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-rw-r--r--src/arch/alpha/faults.cc2
-rw-r--r--src/arch/alpha/faults.hh14
-rw-r--r--src/arch/alpha/isa/mem.isa7
-rw-r--r--src/arch/alpha/isa/pal.isa10
-rw-r--r--src/arch/alpha/tlb.cc12
5 files changed, 23 insertions, 22 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index dae188839..e89cf5c64 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc)
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
if (!tc->misspeculating() &&
- !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
+ reqFlags.none(Request::VPTE|Request::NO_FAULT)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 4b107273b..9d90c7719 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -140,11 +140,11 @@ class DtbFault : public AlphaFault
{
protected:
VAddr vaddr;
- uint32_t reqFlags;
+ Request::Flags reqFlags;
uint64_t flags;
public:
- DtbFault(VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
+ DtbFault(VAddr _vaddr, Request::Flags _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
{ }
FaultName name() const = 0;
@@ -163,7 +163,7 @@ class NDtbMissFault : public DtbFault
static FaultStat _count;
public:
- NDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
@@ -182,7 +182,7 @@ class PDtbMissFault : public DtbFault
static FaultStat _count;
public:
- PDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
@@ -198,7 +198,7 @@ class DtbPageFault : public DtbFault
static FaultStat _count;
public:
- DtbPageFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
@@ -214,7 +214,7 @@ class DtbAcvFault : public DtbFault
static FaultStat _count;
public:
- DtbAcvFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
@@ -230,7 +230,7 @@ class DtbAlignmentFault : public DtbFault
static FaultStat _count;
public:
- DtbAlignmentFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
+ DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
FaultName name() const {return _name;}
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index fe0daf772..b4e10e849 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -43,7 +43,7 @@ output header {{
protected:
/// Memory request flags. See mem_req_base.hh.
- unsigned memAccessFlags;
+ Request::Flags memAccessFlags;
/// Pointer to EAComp object.
const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
@@ -54,7 +54,7 @@ output header {{
StaticInstPtr _eaCompPtr = nullStaticInstPtr,
StaticInstPtr _memAccPtr = nullStaticInstPtr)
: AlphaStaticInst(mnem, _machInst, __opClass),
- memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
+ eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
{
}
@@ -677,7 +677,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
inst_flags)
if mem_flags:
- s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+ mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
+ s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');'
iop.constructor += s
memacc_iop.constructor += s
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 294b92e2f..3d3b81600 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -174,11 +174,11 @@ output decoder {{
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(HW_LDST_DISP)
{
- memAccessFlags = 0;
- if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
- if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
- if (HW_LDST_VPTE) memAccessFlags |= VPTE;
- if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
+ memAccessFlags.clear();
+ if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
+ if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
+ if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
+ if (HW_LDST_LOCK) memAccessFlags.set(Request::LOCKED);
}
std::string
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 9266b8337..be02293d6 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -142,7 +142,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
return new UnimpFault("IPR memory space not implemented!");
} else {
// mark request as uncacheable
- req->setFlags(req->getFlags() | UNCACHEABLE);
+ req->setFlags(Request::UNCACHEABLE);
#if !ALPHA_TLASER
// Clear bits 42:35 of the physical address (10-2 in
@@ -321,7 +321,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC()))
- req->setFlags(req->getFlags() | PHYSICAL);
+ req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) {
// strip off PAL PC marker (lsb is 1)
@@ -330,7 +330,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
return NoFault;
}
- if (req->getFlags() & PHYSICAL) {
+ if (req->getFlags() & Request::PHYSICAL) {
req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
@@ -497,13 +497,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
}
if (PcPAL(pc)) {
- mode = (req->getFlags() & ALTMODE) ?
+ mode = (req->getFlags() & Request::ALTMODE) ?
(mode_type)ALT_MODE_AM(
tc->readMiscRegNoEffect(IPR_ALT_MODE))
: mode_kernel;
}
- if (req->getFlags() & PHYSICAL) {
+ if (req->getFlags() & Request::PHYSICAL) {
req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
@@ -560,7 +560,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (write) { write_misses++; } else { read_misses++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK;
- return (req->getFlags() & VPTE) ?
+ return (req->getFlags() & Request::VPTE) ?
(Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
flags)) :
(Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 15:18:51 +0000