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-rw-r--r--src/arch/alpha/isa/mem.isa2
-rw-r--r--src/arch/alpha/locked_mem.hh4
-rw-r--r--src/arch/alpha/types.hh1
3 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 3a177d990..fe0daf772 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -544,7 +544,7 @@ def template StoreCondCompleteAcc {{
%(fp_enable_check)s;
%(op_dest_decl)s;
- uint64_t write_result = pkt->req->getScResult();
+ uint64_t write_result = pkt->req->getExtraData();
if (fault == NoFault) {
%(postacc_code)s;
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index be5086bd7..56b5ba5ed 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -68,7 +68,7 @@ handleLockedWrite(XC *xc, Request *req)
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
// result register (see stq_c in decoder.isa)
- req->setScResult(2);
+ req->setExtraData(2);
} else {
// standard store conditional
bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
@@ -76,7 +76,7 @@ handleLockedWrite(XC *xc, Request *req)
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
- req->setScResult(0);
+ req->setExtraData(0);
xc->setMiscReg(MISCREG_LOCKFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index ae42552d8..6433ea3ca 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -42,6 +42,7 @@ namespace AlphaISA
typedef uint8_t RegIndex;
typedef uint64_t IntReg;
+ typedef uint64_t LargestRead;
// floating point register file entry type
typedef double FloatReg;