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-rw-r--r--src/arch/alpha/ev5.cc2
-rw-r--r--src/arch/alpha/interrupts.hh8
-rw-r--r--src/arch/alpha/isa/decoder.isa4
-rw-r--r--src/arch/alpha/isa_traits.hh80
-rw-r--r--src/arch/alpha/process.cc7
-rw-r--r--src/arch/alpha/stacktrace.hh8
6 files changed, 56 insertions, 53 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 02497e282..adbebb346 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -351,7 +351,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
case IPR_IPLR:
#ifdef DEBUG
- if (break_ipl != -1 && break_ipl == (val & 0x1f))
+ if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
debug_break();
#endif
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index f8e0ad4ef..3200201db 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -139,14 +139,14 @@ class Interrupts : public SimObject
Fault
getInterrupt(ThreadContext *tc)
{
- int ipl = 0;
- int summary = 0;
+ uint64_t ipl = 0;
+ uint64_t summary = 0;
if (tc->readMiscRegNoEffect(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
if (tc->readMiscRegNoEffect(IPR_SIRR)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
+ for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
@@ -158,7 +158,7 @@ class Interrupts : public SimObject
uint64_t interrupts = intstatus;
if (interrupts) {
- for (int i = INTLEVEL_EXTERNAL_MIN;
+ for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
i < INTLEVEL_EXTERNAL_MAX; i++) {
if (interrupts & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 278ce31e8..cb43fcb74 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -114,7 +114,7 @@ decode OPCODE default Unknown::unknown() {
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{
- uint32_t tmp = Ra.sl + Rb_or_imm.sl;
+ int32_t tmp = Ra.sl + Rb_or_imm.sl;
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
0x49: sublv({{
- uint32_t tmp = Ra.sl - Rb_or_imm.sl;
+ int32_t tmp = Ra.sl - Rb_or_imm.sl;
// signed overflow detection is same as for add,
// except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index f7114e5cc..c8d6f33f9 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -127,45 +127,47 @@ enum mode_type
// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-const int NumPALShadowRegs = 8;
-const int NumFloatArchRegs = 32;
-// @todo: Figure out what this number really should be.
-const int NumMiscArchRegs = 77;
-
-const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-const int NumMiscRegs = NumMiscArchRegs;
-
-const int TotalNumRegs =
- NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
-
-const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-// semantically meaningful register indices
-const int ZeroReg = 31; // architecturally meaningful
-// the rest of these depend on the ABI
-const int StackPointerReg = 30;
-const int GlobalPointerReg = 29;
-const int ProcedureValueReg = 27;
-const int ReturnAddressReg = 26;
-const int ReturnValueReg = 0;
-const int FramePointerReg = 15;
-
-const int SyscallNumReg = 0;
-const int FirstArgumentReg = 16;
-const int SyscallPseudoReturnReg = 20;
-const int SyscallSuccessReg = 19;
-
-const int LogVMPageSize = 13; // 8K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
-const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
-const int MachineBytes = 8;
-const int WordBytes = 4;
-const int HalfwordBytes = 2;
-const int ByteBytes = 1;
+enum {
+ NumIntArchRegs = 32,
+ NumPALShadowRegs = 8,
+ NumFloatArchRegs = 32,
+ // @todo: Figure out what this number really should be.
+ NumMiscArchRegs = 77,
+
+ NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
+ NumFloatRegs = NumFloatArchRegs,
+ NumMiscRegs = NumMiscArchRegs,
+
+ TotalNumRegs =
+ NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs,
+
+ TotalDataRegs = NumIntRegs + NumFloatRegs,
+
+ // semantically meaningful register indices
+ ZeroReg = 31, // architecturally meaningful
+ // the rest of these depend on the ABI
+ StackPointerReg = 30,
+ GlobalPointerReg = 29,
+ ProcedureValueReg = 27,
+ ReturnAddressReg = 26,
+ ReturnValueReg = 0,
+ FramePointerReg = 15,
+
+ SyscallNumReg = 0,
+ FirstArgumentReg = 16,
+ SyscallPseudoReturnReg = 20,
+ SyscallSuccessReg = 19,
+
+ LogVMPageSize = 13, // 8K bytes
+ VMPageSize = (1 << LogVMPageSize),
+
+ BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
+
+ MachineBytes = 8,
+ WordBytes = 4,
+ HalfwordBytes = 2,
+ ByteBytes = 1,
+};
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 93df459ae..6aad45da8 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -100,11 +100,11 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
int auxv_array_size = intSize * 2 * (auxv.size() + 1);
int arg_data_size = 0;
- for (int i = 0; i < argv.size(); ++i) {
+ for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
arg_data_size += argv[i].size() + 1;
}
int env_data_size = 0;
- for (int i = 0; i < envp.size(); ++i) {
+ for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
env_data_size += envp[i].size() + 1;
}
@@ -148,8 +148,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
//Copy the aux stuff
- for(int x = 0; x < auxv.size(); x++)
- {
+ for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
(uint8_t*)&(auxv[x].a_type), intSize);
initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh
index db42c4399..c09ab3576 100644
--- a/src/arch/alpha/stacktrace.hh
+++ b/src/arch/alpha/stacktrace.hh
@@ -91,9 +91,11 @@ class StackTrace
public:
const std::vector<Addr> &getstack() const { return stack; }
- static const int user = 1;
- static const int console = 2;
- static const int unknown = 3;
+ enum {
+ user = 1,
+ console = 2,
+ unknown = 3
+ };
#if TRACING_ON
private:
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 04:01:32 +0000