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-rw-r--r--src/arch/alpha/aout_machdep.h42
-rw-r--r--src/arch/alpha/ev5.cc2
-rw-r--r--src/arch/alpha/floatregfile.hh4
-rw-r--r--src/arch/alpha/ipr.cc144
-rw-r--r--src/arch/alpha/ipr.hh152
-rw-r--r--src/arch/alpha/isa_traits.hh14
-rw-r--r--src/arch/alpha/linux/linux.cc40
-rw-r--r--src/arch/alpha/linux/linux.hh30
-rw-r--r--src/arch/alpha/miscregfile.hh10
-rw-r--r--src/arch/alpha/osfpal.cc512
-rw-r--r--src/arch/alpha/pagetable.hh18
-rw-r--r--src/arch/alpha/regfile.hh12
-rw-r--r--src/arch/alpha/remote_gdb.cc26
-rw-r--r--src/arch/alpha/system.cc6
-rw-r--r--src/arch/alpha/tlb.cc2
-rw-r--r--src/arch/alpha/tru64/process.cc10
-rw-r--r--src/arch/alpha/tru64/tru64.cc40
-rw-r--r--src/arch/alpha/tru64/tru64.hh40
18 files changed, 552 insertions, 552 deletions
diff --git a/src/arch/alpha/aout_machdep.h b/src/arch/alpha/aout_machdep.h
index 58991256a..bcf004d05 100644
--- a/src/arch/alpha/aout_machdep.h
+++ b/src/arch/alpha/aout_machdep.h
@@ -36,35 +36,35 @@
/// Funky Alpha 64-bit a.out header used for PAL code.
///
struct aout_exechdr {
- uint16_t magic; ///< magic number
- uint16_t vstamp; ///< version stamp?
- uint16_t bldrev; ///< ???
- uint16_t padcell; ///< padding
- uint64_t tsize; ///< text segment size
- uint64_t dsize; ///< data segment size
- uint64_t bsize; ///< bss segment size
- uint64_t entry; ///< entry point
- uint64_t text_start; ///< text base address
- uint64_t data_start; ///< data base address
- uint64_t bss_start; ///< bss base address
- uint32_t gprmask; ///< GPR mask (unused, AFAIK)
- uint32_t fprmask; ///< FPR mask (unused, AFAIK)
- uint64_t gp_value; ///< global pointer reg value
+ uint16_t magic; ///< magic number
+ uint16_t vstamp; ///< version stamp?
+ uint16_t bldrev; ///< ???
+ uint16_t padcell; ///< padding
+ uint64_t tsize; ///< text segment size
+ uint64_t dsize; ///< data segment size
+ uint64_t bsize; ///< bss segment size
+ uint64_t entry; ///< entry point
+ uint64_t text_start; ///< text base address
+ uint64_t data_start; ///< data base address
+ uint64_t bss_start; ///< bss base address
+ uint32_t gprmask; ///< GPR mask (unused, AFAIK)
+ uint32_t fprmask; ///< FPR mask (unused, AFAIK)
+ uint64_t gp_value; ///< global pointer reg value
};
-#define AOUT_LDPGSZ 8192
+#define AOUT_LDPGSZ 8192
-#define N_GETMAGIC(ex) ((ex).magic)
+#define N_GETMAGIC(ex) ((ex).magic)
#define N_BADMAX
-#define N_TXTADDR(ex) ((ex).text_start)
-#define N_DATADDR(ex) ((ex).data_start)
-#define N_BSSADDR(ex) ((ex).bss_start)
+#define N_TXTADDR(ex) ((ex).text_start)
+#define N_DATADDR(ex) ((ex).data_start)
+#define N_BSSADDR(ex) ((ex).bss_start)
-#define N_TXTOFF(ex) \
+#define N_TXTOFF(ex) \
(N_GETMAGIC(ex) == ZMAGIC ? 0 : sizeof(struct aout_exechdr))
-#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize)
+#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize)
#endif /* !__AOUT_MACHDEP_H__*/
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 5dc49623e..33306d6af 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -176,7 +176,7 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
AlphaISA::MiscReg
AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
- uint64_t retval = 0; // return value, default 0
+ uint64_t retval = 0; // return value, default 0
switch (idx) {
case AlphaISA::IPR_PALtemp0:
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index 0c5fe17a7..e69e8d186 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -52,8 +52,8 @@ namespace AlphaISA
public:
union {
- uint64_t q[NumFloatRegs]; // integer qword view
- double d[NumFloatRegs]; // double-precision floating point view
+ uint64_t q[NumFloatRegs]; // integer qword view
+ double d[NumFloatRegs]; // double-precision floating point view
};
void serialize(std::ostream &os);
diff --git a/src/arch/alpha/ipr.cc b/src/arch/alpha/ipr.cc
index 8e83102eb..a76fcc2bc 100644
--- a/src/arch/alpha/ipr.cc
+++ b/src/arch/alpha/ipr.cc
@@ -38,89 +38,89 @@ namespace AlphaISA
md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] =
{
//Write only
- RAW_IPR_HWINT_CLR, // H/W interrupt clear register
- RAW_IPR_SL_XMIT, // serial line transmit register
+ RAW_IPR_HWINT_CLR, // H/W interrupt clear register
+ RAW_IPR_SL_XMIT, // serial line transmit register
RAW_IPR_DC_FLUSH,
- RAW_IPR_IC_FLUSH, // instruction cache flush control
- RAW_IPR_ALT_MODE, // alternate mode register
- RAW_IPR_DTB_IA, // DTLB invalidate all register
- RAW_IPR_DTB_IAP, // DTLB invalidate all process register
- RAW_IPR_ITB_IA, // ITLB invalidate all register
- RAW_IPR_ITB_IAP, // ITLB invalidate all process register
+ RAW_IPR_IC_FLUSH, // instruction cache flush control
+ RAW_IPR_ALT_MODE, // alternate mode register
+ RAW_IPR_DTB_IA, // DTLB invalidate all register
+ RAW_IPR_DTB_IAP, // DTLB invalidate all process register
+ RAW_IPR_ITB_IA, // ITLB invalidate all register
+ RAW_IPR_ITB_IAP, // ITLB invalidate all process register
//Read only
- RAW_IPR_INTID, // interrupt ID register
- RAW_IPR_SL_RCV, // serial line receive register
- RAW_IPR_MM_STAT, // data MMU fault status register
- RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register
- RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register
+ RAW_IPR_INTID, // interrupt ID register
+ RAW_IPR_SL_RCV, // serial line receive register
+ RAW_IPR_MM_STAT, // data MMU fault status register
+ RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register
+ RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register
- RAW_IPR_ISR, // interrupt summary register
- RAW_IPR_ITB_TAG, // ITLB tag register
- RAW_IPR_ITB_PTE, // ITLB page table entry register
- RAW_IPR_ITB_ASN, // ITLB address space register
- RAW_IPR_ITB_IS, // ITLB invalidate select register
- RAW_IPR_SIRR, // software interrupt request register
- RAW_IPR_ASTRR, // asynchronous system trap request register
- RAW_IPR_ASTER, // asynchronous system trap enable register
- RAW_IPR_EXC_ADDR, // exception address register
- RAW_IPR_EXC_SUM, // exception summary register
- RAW_IPR_EXC_MASK, // exception mask register
- RAW_IPR_PAL_BASE, // PAL base address register
- RAW_IPR_ICM, // instruction current mode
- RAW_IPR_IPLR, // interrupt priority level register
- RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register
- RAW_IPR_IVPTBR, // virtual page table base register
- RAW_IPR_ICSR, // instruction control and status register
- RAW_IPR_IC_PERR_STAT, // inst cache parity error status register
- RAW_IPR_PMCTR, // performance counter register
+ RAW_IPR_ISR, // interrupt summary register
+ RAW_IPR_ITB_TAG, // ITLB tag register
+ RAW_IPR_ITB_PTE, // ITLB page table entry register
+ RAW_IPR_ITB_ASN, // ITLB address space register
+ RAW_IPR_ITB_IS, // ITLB invalidate select register
+ RAW_IPR_SIRR, // software interrupt request register
+ RAW_IPR_ASTRR, // asynchronous system trap request register
+ RAW_IPR_ASTER, // asynchronous system trap enable register
+ RAW_IPR_EXC_ADDR, // exception address register
+ RAW_IPR_EXC_SUM, // exception summary register
+ RAW_IPR_EXC_MASK, // exception mask register
+ RAW_IPR_PAL_BASE, // PAL base address register
+ RAW_IPR_ICM, // instruction current mode
+ RAW_IPR_IPLR, // interrupt priority level register
+ RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register
+ RAW_IPR_IVPTBR, // virtual page table base register
+ RAW_IPR_ICSR, // instruction control and status register
+ RAW_IPR_IC_PERR_STAT, // inst cache parity error status register
+ RAW_IPR_PMCTR, // performance counter register
// PAL temporary registers...
// register meanings gleaned from osfpal.s source code
- RAW_IPR_PALtemp0, // local scratch
- RAW_IPR_PALtemp1, // local scratch
- RAW_IPR_PALtemp2, // entUna
- RAW_IPR_PALtemp3, // CPU specific impure area pointer
- RAW_IPR_PALtemp4, // memory management temp
- RAW_IPR_PALtemp5, // memory management temp
- RAW_IPR_PALtemp6, // memory management temp
- RAW_IPR_PALtemp7, // entIF
- RAW_IPR_PALtemp8, // intmask
- RAW_IPR_PALtemp9, // entSys
- RAW_IPR_PALtemp10, // ??
- RAW_IPR_PALtemp11, // entInt
- RAW_IPR_PALtemp12, // entArith
- RAW_IPR_PALtemp13, // reserved for platform specific PAL
- RAW_IPR_PALtemp14, // reserved for platform specific PAL
- RAW_IPR_PALtemp15, // reserved for platform specific PAL
- RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0>
- RAW_IPR_PALtemp17, // sysval
- RAW_IPR_PALtemp18, // usp
- RAW_IPR_PALtemp19, // ksp
- RAW_IPR_PALtemp20, // PTBR
- RAW_IPR_PALtemp21, // entMM
- RAW_IPR_PALtemp22, // kgp
- RAW_IPR_PALtemp23, // PCBB
+ RAW_IPR_PALtemp0, // local scratch
+ RAW_IPR_PALtemp1, // local scratch
+ RAW_IPR_PALtemp2, // entUna
+ RAW_IPR_PALtemp3, // CPU specific impure area pointer
+ RAW_IPR_PALtemp4, // memory management temp
+ RAW_IPR_PALtemp5, // memory management temp
+ RAW_IPR_PALtemp6, // memory management temp
+ RAW_IPR_PALtemp7, // entIF
+ RAW_IPR_PALtemp8, // intmask
+ RAW_IPR_PALtemp9, // entSys
+ RAW_IPR_PALtemp10, // ??
+ RAW_IPR_PALtemp11, // entInt
+ RAW_IPR_PALtemp12, // entArith
+ RAW_IPR_PALtemp13, // reserved for platform specific PAL
+ RAW_IPR_PALtemp14, // reserved for platform specific PAL
+ RAW_IPR_PALtemp15, // reserved for platform specific PAL
+ RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0>
+ RAW_IPR_PALtemp17, // sysval
+ RAW_IPR_PALtemp18, // usp
+ RAW_IPR_PALtemp19, // ksp
+ RAW_IPR_PALtemp20, // PTBR
+ RAW_IPR_PALtemp21, // entMM
+ RAW_IPR_PALtemp22, // kgp
+ RAW_IPR_PALtemp23, // PCBB
- RAW_IPR_DTB_ASN, // DTLB address space number register
- RAW_IPR_DTB_CM, // DTLB current mode register
- RAW_IPR_DTB_TAG, // DTLB tag register
- RAW_IPR_DTB_PTE, // DTLB page table entry register
+ RAW_IPR_DTB_ASN, // DTLB address space number register
+ RAW_IPR_DTB_CM, // DTLB current mode register
+ RAW_IPR_DTB_TAG, // DTLB tag register
+ RAW_IPR_DTB_PTE, // DTLB page table entry register
- RAW_IPR_VA, // fault virtual address register
- RAW_IPR_VA_FORM, // formatted virtual address register
- RAW_IPR_MVPTBR, // MTU virtual page table base register
- RAW_IPR_DTB_IS, // DTLB invalidate single register
- RAW_IPR_CC, // cycle counter register
- RAW_IPR_CC_CTL, // cycle counter control register
- RAW_IPR_MCSR, // MTU control register
+ RAW_IPR_VA, // fault virtual address register
+ RAW_IPR_VA_FORM, // formatted virtual address register
+ RAW_IPR_MVPTBR, // MTU virtual page table base register
+ RAW_IPR_DTB_IS, // DTLB invalidate single register
+ RAW_IPR_CC, // cycle counter register
+ RAW_IPR_CC_CTL, // cycle counter control register
+ RAW_IPR_MCSR, // MTU control register
- RAW_IPR_DC_PERR_STAT, // Dcache parity error status register
- RAW_IPR_DC_TEST_CTL, // Dcache test tag control register
- RAW_IPR_DC_TEST_TAG, // Dcache test tag register
+ RAW_IPR_DC_PERR_STAT, // Dcache parity error status register
+ RAW_IPR_DC_TEST_CTL, // Dcache test tag control register
+ RAW_IPR_DC_TEST_TAG, // Dcache test tag register
RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register
- RAW_IPR_DC_MODE, // Dcache mode register
- RAW_IPR_MAF_MODE // miss address file mode register
+ RAW_IPR_DC_MODE, // Dcache mode register
+ RAW_IPR_MAF_MODE // miss address file mode register
};
int IprToMiscRegIndex[MaxInternalProcRegs];
diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh
index b55154764..6296cdb9a 100644
--- a/src/arch/alpha/ipr.hh
+++ b/src/arch/alpha/ipr.hh
@@ -40,88 +40,88 @@ namespace AlphaISA
//
enum md_ipr_names
{
- RAW_IPR_ISR = 0x100, // interrupt summary register
- RAW_IPR_ITB_TAG = 0x101, // ITLB tag register
- RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register
- RAW_IPR_ITB_ASN = 0x103, // ITLB address space register
- RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
- RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register
- RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
- RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register
- RAW_IPR_SIRR = 0x108, // software interrupt request register
- RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register
- RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register
- RAW_IPR_EXC_ADDR = 0x10b, // exception address register
- RAW_IPR_EXC_SUM = 0x10c, // exception summary register
- RAW_IPR_EXC_MASK = 0x10d, // exception mask register
- RAW_IPR_PAL_BASE = 0x10e, // PAL base address register
- RAW_IPR_ICM = 0x10f, // instruction current mode
- RAW_IPR_IPLR = 0x110, // interrupt priority level register
- RAW_IPR_INTID = 0x111, // interrupt ID register
- RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
- RAW_IPR_IVPTBR = 0x113, // virtual page table base register
- RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
- RAW_IPR_SL_XMIT = 0x116, // serial line transmit register
- RAW_IPR_SL_RCV = 0x117, // serial line receive register
- RAW_IPR_ICSR = 0x118, // instruction control and status register
- RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
- RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
- RAW_IPR_PMCTR = 0x11c, // performance counter register
+ RAW_IPR_ISR = 0x100, // interrupt summary register
+ RAW_IPR_ITB_TAG = 0x101, // ITLB tag register
+ RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register
+ RAW_IPR_ITB_ASN = 0x103, // ITLB address space register
+ RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
+ RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register
+ RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
+ RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register
+ RAW_IPR_SIRR = 0x108, // software interrupt request register
+ RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register
+ RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register
+ RAW_IPR_EXC_ADDR = 0x10b, // exception address register
+ RAW_IPR_EXC_SUM = 0x10c, // exception summary register
+ RAW_IPR_EXC_MASK = 0x10d, // exception mask register
+ RAW_IPR_PAL_BASE = 0x10e, // PAL base address register
+ RAW_IPR_ICM = 0x10f, // instruction current mode
+ RAW_IPR_IPLR = 0x110, // interrupt priority level register
+ RAW_IPR_INTID = 0x111, // interrupt ID register
+ RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
+ RAW_IPR_IVPTBR = 0x113, // virtual page table base register
+ RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
+ RAW_IPR_SL_XMIT = 0x116, // serial line transmit register
+ RAW_IPR_SL_RCV = 0x117, // serial line receive register
+ RAW_IPR_ICSR = 0x118, // instruction control and status register
+ RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
+ RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
+ RAW_IPR_PMCTR = 0x11c, // performance counter register
// PAL temporary registers...
// register meanings gleaned from osfpal.s source code
- RAW_IPR_PALtemp0 = 0x140, // local scratch
- RAW_IPR_PALtemp1 = 0x141, // local scratch
- RAW_IPR_PALtemp2 = 0x142, // entUna
- RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
- RAW_IPR_PALtemp4 = 0x144, // memory management temp
- RAW_IPR_PALtemp5 = 0x145, // memory management temp
- RAW_IPR_PALtemp6 = 0x146, // memory management temp
- RAW_IPR_PALtemp7 = 0x147, // entIF
- RAW_IPR_PALtemp8 = 0x148, // intmask
- RAW_IPR_PALtemp9 = 0x149, // entSys
- RAW_IPR_PALtemp10 = 0x14a, // ??
- RAW_IPR_PALtemp11 = 0x14b, // entInt
- RAW_IPR_PALtemp12 = 0x14c, // entArith
- RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
- RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
- RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
- RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
- RAW_IPR_PALtemp17 = 0x151, // sysval
- RAW_IPR_PALtemp18 = 0x152, // usp
- RAW_IPR_PALtemp19 = 0x153, // ksp
- RAW_IPR_PALtemp20 = 0x154, // PTBR
- RAW_IPR_PALtemp21 = 0x155, // entMM
- RAW_IPR_PALtemp22 = 0x156, // kgp
- RAW_IPR_PALtemp23 = 0x157, // PCBB
-
- RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register
- RAW_IPR_DTB_CM = 0x201, // DTLB current mode register
- RAW_IPR_DTB_TAG = 0x202, // DTLB tag register
- RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register
- RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
-
- RAW_IPR_MM_STAT = 0x205, // data MMU fault status register
- RAW_IPR_VA = 0x206, // fault virtual address register
- RAW_IPR_VA_FORM = 0x207, // formatted virtual address register
- RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register
- RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
- RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register
- RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register
- RAW_IPR_ALT_MODE = 0x20c, // alternate mode register
- RAW_IPR_CC = 0x20d, // cycle counter register
- RAW_IPR_CC_CTL = 0x20e, // cycle counter control register
- RAW_IPR_MCSR = 0x20f, // MTU control register
+ RAW_IPR_PALtemp0 = 0x140, // local scratch
+ RAW_IPR_PALtemp1 = 0x141, // local scratch
+ RAW_IPR_PALtemp2 = 0x142, // entUna
+ RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
+ RAW_IPR_PALtemp4 = 0x144, // memory management temp
+ RAW_IPR_PALtemp5 = 0x145, // memory management temp
+ RAW_IPR_PALtemp6 = 0x146, // memory management temp
+ RAW_IPR_PALtemp7 = 0x147, // entIF
+ RAW_IPR_PALtemp8 = 0x148, // intmask
+ RAW_IPR_PALtemp9 = 0x149, // entSys
+ RAW_IPR_PALtemp10 = 0x14a, // ??
+ RAW_IPR_PALtemp11 = 0x14b, // entInt
+ RAW_IPR_PALtemp12 = 0x14c, // entArith
+ RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
+ RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
+ RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
+ RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
+ RAW_IPR_PALtemp17 = 0x151, // sysval
+ RAW_IPR_PALtemp18 = 0x152, // usp
+ RAW_IPR_PALtemp19 = 0x153, // ksp
+ RAW_IPR_PALtemp20 = 0x154, // PTBR
+ RAW_IPR_PALtemp21 = 0x155, // entMM
+ RAW_IPR_PALtemp22 = 0x156, // kgp
+ RAW_IPR_PALtemp23 = 0x157, // PCBB
+
+ RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register
+ RAW_IPR_DTB_CM = 0x201, // DTLB current mode register
+ RAW_IPR_DTB_TAG = 0x202, // DTLB tag register
+ RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register
+ RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
+
+ RAW_IPR_MM_STAT = 0x205, // data MMU fault status register
+ RAW_IPR_VA = 0x206, // fault virtual address register
+ RAW_IPR_VA_FORM = 0x207, // formatted virtual address register
+ RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register
+ RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
+ RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register
+ RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register
+ RAW_IPR_ALT_MODE = 0x20c, // alternate mode register
+ RAW_IPR_CC = 0x20d, // cycle counter register
+ RAW_IPR_CC_CTL = 0x20e, // cycle counter control register
+ RAW_IPR_MCSR = 0x20f, // MTU control register
RAW_IPR_DC_FLUSH = 0x210,
- RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
- RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
- RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
+ RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
+ RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
+ RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
- RAW_IPR_DC_MODE = 0x216, // Dcache mode register
- RAW_IPR_MAF_MODE = 0x217, // miss address file mode register
+ RAW_IPR_DC_MODE = 0x216, // Dcache mode register
+ RAW_IPR_MAF_MODE = 0x217, // miss address file mode register
- MaxInternalProcRegs // number of IPR registers
+ MaxInternalProcRegs // number of IPR registers
};
enum MiscRegIpr
@@ -215,7 +215,7 @@ namespace AlphaISA
IPR_DC_MODE,
IPR_MAF_MODE,
- NumInternalProcRegs // number of IPR registers
+ NumInternalProcRegs // number of IPR registers
};
inline bool IprIsWritable(int index)
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index be1d1b8bb..4837d4a34 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -123,11 +123,11 @@ namespace AlphaISA
// EV5 modes
enum mode_type
{
- mode_kernel = 0, // kernel
- mode_executive = 1, // executive (unused by unix)
- mode_supervisor = 2, // supervisor (unused by unix)
- mode_user = 3, // user mode
- mode_number // number of modes
+ mode_kernel = 0, // kernel
+ mode_executive = 1, // executive (unused by unix)
+ mode_supervisor = 2, // supervisor (unused by unix)
+ mode_user = 3, // user mode
+ mode_number // number of modes
};
// Constants Related to the number of registers
@@ -148,7 +148,7 @@ namespace AlphaISA
const int TotalDataRegs = NumIntRegs + NumFloatRegs;
// semantically meaningful register indices
- const int ZeroReg = 31; // architecturally meaningful
+ const int ZeroReg = 31; // architecturally meaningful
// the rest of these depend on the ABI
const int StackPointerReg = 30;
const int GlobalPointerReg = 29;
@@ -164,7 +164,7 @@ namespace AlphaISA
const int SyscallPseudoReturnReg = ArgumentReg[4];
const int SyscallSuccessReg = 19;
- const int LogVMPageSize = 13; // 8K bytes
+ const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
diff --git a/src/arch/alpha/linux/linux.cc b/src/arch/alpha/linux/linux.cc
index e6908a572..3e80f62a7 100644
--- a/src/arch/alpha/linux/linux.cc
+++ b/src/arch/alpha/linux/linux.cc
@@ -35,34 +35,34 @@
// open(2) flags translation table
OpenFlagTransTable AlphaLinux::openFlagTable[] = {
#ifdef _MSC_VER
- { AlphaLinux::TGT_O_RDONLY, _O_RDONLY },
- { AlphaLinux::TGT_O_WRONLY, _O_WRONLY },
- { AlphaLinux::TGT_O_RDWR, _O_RDWR },
- { AlphaLinux::TGT_O_APPEND, _O_APPEND },
- { AlphaLinux::TGT_O_CREAT, _O_CREAT },
- { AlphaLinux::TGT_O_TRUNC, _O_TRUNC },
- { AlphaLinux::TGT_O_EXCL, _O_EXCL },
+ { AlphaLinux::TGT_O_RDONLY, _O_RDONLY },
+ { AlphaLinux::TGT_O_WRONLY, _O_WRONLY },
+ { AlphaLinux::TGT_O_RDWR, _O_RDWR },
+ { AlphaLinux::TGT_O_APPEND, _O_APPEND },
+ { AlphaLinux::TGT_O_CREAT, _O_CREAT },
+ { AlphaLinux::TGT_O_TRUNC, _O_TRUNC },
+ { AlphaLinux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
- { AlphaLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
+ { AlphaLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
- { AlphaLinux::TGT_O_NOCTTY, _O_NOCTTY },
+ { AlphaLinux::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
- { AlphaLinux::TGT_O_SYNC, _O_SYNC },
+ { AlphaLinux::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
- { AlphaLinux::TGT_O_RDONLY, O_RDONLY },
- { AlphaLinux::TGT_O_WRONLY, O_WRONLY },
- { AlphaLinux::TGT_O_RDWR, O_RDWR },
- { AlphaLinux::TGT_O_APPEND, O_APPEND },
- { AlphaLinux::TGT_O_CREAT, O_CREAT },
- { AlphaLinux::TGT_O_TRUNC, O_TRUNC },
- { AlphaLinux::TGT_O_EXCL, O_EXCL },
- { AlphaLinux::TGT_O_NONBLOCK, O_NONBLOCK },
- { AlphaLinux::TGT_O_NOCTTY, O_NOCTTY },
+ { AlphaLinux::TGT_O_RDONLY, O_RDONLY },
+ { AlphaLinux::TGT_O_WRONLY, O_WRONLY },
+ { AlphaLinux::TGT_O_RDWR, O_RDWR },
+ { AlphaLinux::TGT_O_APPEND, O_APPEND },
+ { AlphaLinux::TGT_O_CREAT, O_CREAT },
+ { AlphaLinux::TGT_O_TRUNC, O_TRUNC },
+ { AlphaLinux::TGT_O_EXCL, O_EXCL },
+ { AlphaLinux::TGT_O_NONBLOCK, O_NONBLOCK },
+ { AlphaLinux::TGT_O_NOCTTY, O_NOCTTY },
#ifdef O_SYNC
- { AlphaLinux::TGT_O_SYNC, O_SYNC },
+ { AlphaLinux::TGT_O_SYNC, O_SYNC },
#endif
#endif /* _MSC_VER */
};
diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh
index 84c04ebc3..803970aa9 100644
--- a/src/arch/alpha/linux/linux.hh
+++ b/src/arch/alpha/linux/linux.hh
@@ -50,21 +50,21 @@ class AlphaLinux : public Linux
//@{
/// open(2) flag values.
- static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
- static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
- static const int TGT_O_RDWR = 00000002; //!< O_RDWR
- static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
- static const int TGT_O_APPEND = 00000010; //!< O_APPEND
- static const int TGT_O_CREAT = 00001000; //!< O_CREAT
- static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
- static const int TGT_O_EXCL = 00004000; //!< O_EXCL
- static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
- static const int TGT_O_SYNC = 00040000; //!< O_SYNC
- static const int TGT_O_DRD = 00100000; //!< O_DRD
- static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
- static const int TGT_O_CACHE = 00400000; //!< O_CACHE
- static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
- static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
+ static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
+ static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
+ static const int TGT_O_RDWR = 00000002; //!< O_RDWR
+ static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
+ static const int TGT_O_APPEND = 00000010; //!< O_APPEND
+ static const int TGT_O_CREAT = 00001000; //!< O_CREAT
+ static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
+ static const int TGT_O_EXCL = 00004000; //!< O_EXCL
+ static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
+ static const int TGT_O_SYNC = 00040000; //!< O_SYNC
+ static const int TGT_O_DRD = 00100000; //!< O_DRD
+ static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
+ static const int TGT_O_CACHE = 00400000; //!< O_CACHE
+ static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
+ static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
//@}
/// For mmap().
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 022b6404a..f07b998e6 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -60,11 +60,11 @@ namespace AlphaISA
class MiscRegFile {
protected:
- uint64_t fpcr; // floating point condition codes
- uint64_t uniq; // process-unique register
- bool lock_flag; // lock flag for LL/SC
- Addr lock_addr; // lock address for LL/SC
- int intr_flag;
+ uint64_t fpcr; // floating point condition codes
+ uint64_t uniq; // process-unique register
+ bool lock_flag; // lock flag for LL/SC
+ Addr lock_addr; // lock address for LL/SC
+ int intr_flag;
public:
MiscRegFile()
diff --git a/src/arch/alpha/osfpal.cc b/src/arch/alpha/osfpal.cc
index ed1d255a6..0edbadb06 100644
--- a/src/arch/alpha/osfpal.cc
+++ b/src/arch/alpha/osfpal.cc
@@ -33,265 +33,265 @@
namespace {
const char *strings[PAL::NumCodes] = {
// Priviledged PAL instructions
- "halt", // 0x00
- "cflush", // 0x01
- "draina", // 0x02
- 0, // 0x03
- 0, // 0x04
- 0, // 0x05
- 0, // 0x06
- 0, // 0x07
- 0, // 0x08
- "cserve", // 0x09
- "swppal", // 0x0a
- 0, // 0x0b
- 0, // 0x0c
- "wripir", // 0x0d
- 0, // 0x0e
- 0, // 0x0f
- "rdmces", // 0x10
- "wrmces", // 0x11
- 0, // 0x12
- 0, // 0x13
- 0, // 0x14
- 0, // 0x15
- 0, // 0x16
- 0, // 0x17
- 0, // 0x18
- 0, // 0x19
- 0, // 0x1a
- 0, // 0x1b
- 0, // 0x1c
- 0, // 0x1d
- 0, // 0x1e
- 0, // 0x1f
- 0, // 0x20
- 0, // 0x21
- 0, // 0x22
- 0, // 0x23
- 0, // 0x24
- 0, // 0x25
- 0, // 0x26
- 0, // 0x27
- 0, // 0x28
- 0, // 0x29
- 0, // 0x2a
- "wrfen", // 0x2b
- 0, // 0x2c
- "wrvptptr", // 0x2d
- 0, // 0x2e
- 0, // 0x2f
- "swpctx", // 0x30
- "wrval", // 0x31
- "rdval", // 0x32
- "tbi", // 0x33
- "wrent", // 0x34
- "swpipl", // 0x35
- "rdps", // 0x36
- "wrkgp", // 0x37
- "wrusp", // 0x38
- "wrperfmon", // 0x39
- "rdusp", // 0x3a
- 0, // 0x3b
- "whami", // 0x3c
- "retsys", // 0x3d
- "wtint", // 0x3e
- "rti", // 0x3f
- 0, // 0x40
- 0, // 0x41
- 0, // 0x42
- 0, // 0x43
- 0, // 0x44
- 0, // 0x45
- 0, // 0x46
- 0, // 0x47
- 0, // 0x48
- 0, // 0x49
- 0, // 0x4a
- 0, // 0x4b
- 0, // 0x4c
- 0, // 0x4d
- 0, // 0x4e
- 0, // 0x4f
- 0, // 0x50
- 0, // 0x51
- 0, // 0x52
- 0, // 0x53
- 0, // 0x54
- 0, // 0x55
- 0, // 0x56
- 0, // 0x57
- 0, // 0x58
- 0, // 0x59
- 0, // 0x5a
- 0, // 0x5b
- 0, // 0x5c
- 0, // 0x5d
- 0, // 0x5e
- 0, // 0x5f
- 0, // 0x60
- 0, // 0x61
- 0, // 0x62
- 0, // 0x63
- 0, // 0x64
- 0, // 0x65
- 0, // 0x66
- 0, // 0x67
- 0, // 0x68
- 0, // 0x69
- 0, // 0x6a
- 0, // 0x6b
- 0, // 0x6c
- 0, // 0x6d
- 0, // 0x6e
- 0, // 0x6f
- 0, // 0x70
- 0, // 0x71
- 0, // 0x72
- 0, // 0x73
- 0, // 0x74
- 0, // 0x75
- 0, // 0x76
- 0, // 0x77
- 0, // 0x78
- 0, // 0x79
- 0, // 0x7a
- 0, // 0x7b
- 0, // 0x7c
- 0, // 0x7d
- 0, // 0x7e
- 0, // 0x7f
+ "halt", // 0x00
+ "cflush", // 0x01
+ "draina", // 0x02
+ 0, // 0x03
+ 0, // 0x04
+ 0, // 0x05
+ 0, // 0x06
+ 0, // 0x07
+ 0, // 0x08
+ "cserve", // 0x09
+ "swppal", // 0x0a
+ 0, // 0x0b
+ 0, // 0x0c
+ "wripir", // 0x0d
+ 0, // 0x0e
+ 0, // 0x0f
+ "rdmces", // 0x10
+ "wrmces", // 0x11
+ 0, // 0x12
+ 0, // 0x13
+ 0, // 0x14
+ 0, // 0x15
+ 0, // 0x16
+ 0, // 0x17
+ 0, // 0x18
+ 0, // 0x19
+ 0, // 0x1a
+ 0, // 0x1b
+ 0, // 0x1c
+ 0, // 0x1d
+ 0, // 0x1e
+ 0, // 0x1f
+ 0, // 0x20
+ 0, // 0x21
+ 0, // 0x22
+ 0, // 0x23
+ 0, // 0x24
+ 0, // 0x25
+ 0, // 0x26
+ 0, // 0x27
+ 0, // 0x28
+ 0, // 0x29
+ 0, // 0x2a
+ "wrfen", // 0x2b
+ 0, // 0x2c
+ "wrvptptr", // 0x2d
+ 0, // 0x2e
+ 0, // 0x2f
+ "swpctx", // 0x30
+ "wrval", // 0x31
+ "rdval", // 0x32
+ "tbi", // 0x33
+ "wrent", // 0x34
+ "swpipl", // 0x35
+ "rdps", // 0x36
+ "wrkgp", // 0x37
+ "wrusp", // 0x38
+ "wrperfmon", // 0x39
+ "rdusp", // 0x3a
+ 0, // 0x3b
+ "whami", // 0x3c
+ "retsys", // 0x3d
+ "wtint", // 0x3e
+ "rti", // 0x3f
+ 0, // 0x40
+ 0, // 0x41
+ 0, // 0x42
+ 0, // 0x43
+ 0, // 0x44
+ 0, // 0x45
+ 0, // 0x46
+ 0, // 0x47
+ 0, // 0x48
+ 0, // 0x49
+ 0, // 0x4a
+ 0, // 0x4b
+ 0, // 0x4c
+ 0, // 0x4d
+ 0, // 0x4e
+ 0, // 0x4f
+ 0, // 0x50
+ 0, // 0x51
+ 0, // 0x52
+ 0, // 0x53
+ 0, // 0x54
+ 0, // 0x55
+ 0, // 0x56
+ 0, // 0x57
+ 0, // 0x58
+ 0, // 0x59
+ 0, // 0x5a
+ 0, // 0x5b
+ 0, // 0x5c
+ 0, // 0x5d
+ 0, // 0x5e
+ 0, // 0x5f
+ 0, // 0x60
+ 0, // 0x61
+ 0, // 0x62
+ 0, // 0x63
+ 0, // 0x64
+ 0, // 0x65
+ 0, // 0x66
+ 0, // 0x67
+ 0, // 0x68
+ 0, // 0x69
+ 0, // 0x6a
+ 0, // 0x6b
+ 0, // 0x6c
+ 0, // 0x6d
+ 0, // 0x6e
+ 0, // 0x6f
+ 0, // 0x70
+ 0, // 0x71
+ 0, // 0x72
+ 0, // 0x73
+ 0, // 0x74
+ 0, // 0x75
+ 0, // 0x76
+ 0, // 0x77
+ 0, // 0x78
+ 0, // 0x79
+ 0, // 0x7a
+ 0, // 0x7b
+ 0, // 0x7c
+ 0, // 0x7d
+ 0, // 0x7e
+ 0, // 0x7f
// Unpriviledged PAL instructions
- "bpt", // 0x80
- "bugchk", // 0x81
- 0, // 0x82
- "callsys", // 0x83
- 0, // 0x84
- 0, // 0x85
- "imb", // 0x86
- 0, // 0x87
- 0, // 0x88
- 0, // 0x89
- 0, // 0x8a
- 0, // 0x8b
- 0, // 0x8c
- 0, // 0x8d
- 0, // 0x8e
- 0, // 0x8f
- 0, // 0x90
- 0, // 0x91
- "urti", // 0x92
- 0, // 0x93
- 0, // 0x94
- 0, // 0x95
- 0, // 0x96
- 0, // 0x97
- 0, // 0x98
- 0, // 0x99
- 0, // 0x9a
- 0, // 0x9b
- 0, // 0x9c
- 0, // 0x9d
- "rdunique", // 0x9e
- "wrunique", // 0x9f
- 0, // 0xa0
- 0, // 0xa1
- 0, // 0xa2
- 0, // 0xa3
- 0, // 0xa4
- 0, // 0xa5
- 0, // 0xa6
- 0, // 0xa7
- 0, // 0xa8
- 0, // 0xa9
- "gentrap", // 0xaa
- 0, // 0xab
- 0, // 0xac
- 0, // 0xad
- "clrfen", // 0xae
- 0, // 0xaf
- 0, // 0xb0
- 0, // 0xb1
- 0, // 0xb2
- 0, // 0xb3
- 0, // 0xb4
- 0, // 0xb5
- 0, // 0xb6
- 0, // 0xb7
- 0, // 0xb8
- 0, // 0xb9
- 0, // 0xba
- 0, // 0xbb
- 0, // 0xbc
- 0, // 0xbd
- "nphalt", // 0xbe
- "copypal", // 0xbf
+ "bpt", // 0x80
+ "bugchk", // 0x81
+ 0, // 0x82
+ "callsys", // 0x83
+ 0, // 0x84
+ 0, // 0x85
+ "imb", // 0x86
+ 0, // 0x87
+ 0, // 0x88
+ 0, // 0x89
+ 0, // 0x8a
+ 0, // 0x8b
+ 0, // 0x8c
+ 0, // 0x8d
+ 0, // 0x8e
+ 0, // 0x8f
+ 0, // 0x90
+ 0, // 0x91
+ "urti", // 0x92
+ 0, // 0x93
+ 0, // 0x94
+ 0, // 0x95
+ 0, // 0x96
+ 0, // 0x97
+ 0, // 0x98
+ 0, // 0x99
+ 0, // 0x9a
+ 0, // 0x9b
+ 0, // 0x9c
+ 0, // 0x9d
+ "rdunique", // 0x9e
+ "wrunique", // 0x9f
+ 0, // 0xa0
+ 0, // 0xa1
+ 0, // 0xa2
+ 0, // 0xa3
+ 0, // 0xa4
+ 0, // 0xa5
+ 0, // 0xa6
+ 0, // 0xa7
+ 0, // 0xa8
+ 0, // 0xa9
+ "gentrap", // 0xaa
+ 0, // 0xab
+ 0, // 0xac
+ 0, // 0xad
+ "clrfen", // 0xae
+ 0, // 0xaf
+ 0, // 0xb0
+ 0, // 0xb1
+ 0, // 0xb2
+ 0, // 0xb3
+ 0, // 0xb4
+ 0, // 0xb5
+ 0, // 0xb6
+ 0, // 0xb7
+ 0, // 0xb8
+ 0, // 0xb9
+ 0, // 0xba
+ 0, // 0xbb
+ 0, // 0xbc
+ 0, // 0xbd
+ "nphalt", // 0xbe
+ "copypal", // 0xbf
#if 0
- 0, // 0xc0
- 0, // 0xc1
- 0, // 0xc2
- 0, // 0xc3
- 0, // 0xc4
- 0, // 0xc5
- 0, // 0xc6
- 0, // 0xc7
- 0, // 0xc8
- 0, // 0xc9
- 0, // 0xca
- 0, // 0xcb
- 0, // 0xcc
- 0, // 0xcd
- 0, // 0xce
- 0, // 0xcf
- 0, // 0xd0
- 0, // 0xd1
- 0, // 0xd2
- 0, // 0xd3
- 0, // 0xd4
- 0, // 0xd5
- 0, // 0xd6
- 0, // 0xd7
- 0, // 0xd8
- 0, // 0xd9
- 0, // 0xda
- 0, // 0xdb
- 0, // 0xdc
- 0, // 0xdd
- 0, // 0xde
- 0, // 0xdf
- 0, // 0xe0
- 0, // 0xe1
- 0, // 0xe2
- 0, // 0xe3
- 0, // 0xe4
- 0, // 0xe5
- 0, // 0xe6
- 0, // 0xe7
- 0, // 0xe8
- 0, // 0xe9
- 0, // 0xea
- 0, // 0xeb
- 0, // 0xec
- 0, // 0xed
- 0, // 0xee
- 0, // 0xef
- 0, // 0xf0
- 0, // 0xf1
- 0, // 0xf2
- 0, // 0xf3
- 0, // 0xf4
- 0, // 0xf5
- 0, // 0xf6
- 0, // 0xf7
- 0, // 0xf8
- 0, // 0xf9
- 0, // 0xfa
- 0, // 0xfb
- 0, // 0xfc
- 0, // 0xfd
- 0, // 0xfe
- 0 // 0xff
+ 0, // 0xc0
+ 0, // 0xc1
+ 0, // 0xc2
+ 0, // 0xc3
+ 0, // 0xc4
+ 0, // 0xc5
+ 0, // 0xc6
+ 0, // 0xc7
+ 0, // 0xc8
+ 0, // 0xc9
+ 0, // 0xca
+ 0, // 0xcb
+ 0, // 0xcc
+ 0, // 0xcd
+ 0, // 0xce
+ 0, // 0xcf
+ 0, // 0xd0
+ 0, // 0xd1
+ 0, // 0xd2
+ 0, // 0xd3
+ 0, // 0xd4
+ 0, // 0xd5
+ 0, // 0xd6
+ 0, // 0xd7
+ 0, // 0xd8
+ 0, // 0xd9
+ 0, // 0xda
+ 0, // 0xdb
+ 0, // 0xdc
+ 0, // 0xdd
+ 0, // 0xde
+ 0, // 0xdf
+ 0, // 0xe0
+ 0, // 0xe1
+ 0, // 0xe2
+ 0, // 0xe3
+ 0, // 0xe4
+ 0, // 0xe5
+ 0, // 0xe6
+ 0, // 0xe7
+ 0, // 0xe8
+ 0, // 0xe9
+ 0, // 0xea
+ 0, // 0xeb
+ 0, // 0xec
+ 0, // 0xed
+ 0, // 0xee
+ 0, // 0xef
+ 0, // 0xf0
+ 0, // 0xf1
+ 0, // 0xf2
+ 0, // 0xf3
+ 0, // 0xf4
+ 0, // 0xf5
+ 0, // 0xf6
+ 0, // 0xf7
+ 0, // 0xf8
+ 0, // 0xf9
+ 0, // 0xfa
+ 0, // 0xfb
+ 0, // 0xfc
+ 0, // 0xfd
+ 0, // 0xfe
+ 0 // 0xff
#endif
};
}
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 8ce5b4e5d..f28c1b195 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -110,15 +110,15 @@ namespace AlphaISA {
TlbEntry()
{}
- Addr tag; // virtual page number tag
- Addr ppn; // physical page number
- uint8_t xre; // read permissions - VMEM_PERM_* mask
- uint8_t xwe; // write permissions - VMEM_PERM_* mask
- uint8_t asn; // address space number
- bool asma; // address space match
- bool fonr; // fault on read
- bool fonw; // fault on write
- bool valid; // valid page table entry
+ Addr tag; // virtual page number tag
+ Addr ppn; // physical page number
+ uint8_t xre; // read permissions - VMEM_PERM_* mask
+ uint8_t xwe; // write permissions - VMEM_PERM_* mask
+ uint8_t asn; // address space number
+ bool asma; // address space match
+ bool fonr; // fault on read
+ bool fonw; // fault on write
+ bool valid; // valid page table entry
Addr pageStart()
{
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 792a518fb..0c1f07bdd 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -51,8 +51,8 @@ namespace AlphaISA
class RegFile {
protected:
- Addr pc; // program counter
- Addr npc; // next-cycle program counter
+ Addr pc; // program counter
+ Addr npc; // next-cycle program counter
Addr nnpc;
public:
@@ -85,14 +85,14 @@ namespace AlphaISA
{ }
protected:
- IntRegFile intRegFile; // (signed) integer register file
- FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
+ IntRegFile intRegFile; // (signed) integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
public:
#if FULL_SYSTEM
- int intrflag; // interrupt flag
+ int intrflag; // interrupt flag
inline int instAsid()
{ return miscRegFile.getInstAsid(); }
inline int dataAsid()
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index ea5db36f4..8d70ebfa2 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -30,7 +30,7 @@
/*
* Copyright (c) 1990, 1993
- * The Regents of the University of California. All rights reserved.
+ * The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
@@ -38,8 +38,8 @@
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Lawrence Berkeley Laboratories.
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratories.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -51,8 +51,8 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
@@ -69,7 +69,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
+ * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
*/
/*-
@@ -89,8 +89,8 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
@@ -151,7 +151,7 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
///////////////////////////////////////////////////////////
// RemoteGDB::acc
//
-// Determine if the mapping at va..(va+len) is valid.
+// Determine if the mapping at va..(va+len) is valid.
//
bool
RemoteGDB::acc(Addr va, size_t len)
@@ -204,8 +204,8 @@ RemoteGDB::acc(Addr va, size_t len)
///////////////////////////////////////////////////////////
// RemoteGDB::getregs
//
-// Translate the kernel debugger register format into
-// the GDB register format.
+// Translate the kernel debugger register format into
+// the GDB register format.
void
RemoteGDB::getregs()
{
@@ -234,8 +234,8 @@ RemoteGDB::getregs()
///////////////////////////////////////////////////////////
// RemoteGDB::setregs
//
-// Translate the GDB register format into the kernel
-// debugger register format.
+// Translate the GDB register format into the kernel
+// debugger register format.
//
void
RemoteGDB::setregs()
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 2af62ceea..f8fea4fee 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -142,9 +142,9 @@ AlphaSystem::~AlphaSystem()
* in the procedure value register (pv aka t12 == r27). This sequence
* looks like the following:
*
- * opcode Ra Rb offset
- * ldah gp,X(pv) 09 29 27 X
- * lda gp,Y(gp) 08 29 29 Y
+ * opcode Ra Rb offset
+ * ldah gp,X(pv) 09 29 27 X
+ * lda gp,Y(gp) 08 29 29 Y
*
* for some constant offsets X and Y. The catch is that the linker
* (or maybe even the compiler, I'm not sure) may recognize that the
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 4f960360e..60502ebdb 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -55,7 +55,7 @@ bool uncacheBit39 = false;
bool uncacheBit40 = false;
#endif
-#define MODE2MASK(X) (1 << (X))
+#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
: BaseTLB(p), size(p->size), nlu(0)
diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc
index e9f7b6be1..5f448489e 100644
--- a/src/arch/alpha/tru64/process.cc
+++ b/src/arch/alpha/tru64/process.cc
@@ -85,7 +85,7 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
case AlphaTru64::GSI_PHYSMEM: {
TypedBufferArg<uint64_t> physmem(tc->getSyscallArg(1));
- *physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
+ *physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
physmem.copyOut(tc->getMemPort());
return 1;
}
@@ -168,11 +168,11 @@ SyscallReturn tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
using namespace std;
using namespace TheISA;
- int id = tc->getSyscallArg(0); // table ID
- int index = tc->getSyscallArg(1); // index into table
+ int id = tc->getSyscallArg(0); // table ID
+ int index = tc->getSyscallArg(1); // index into table
// arg 2 is buffer pointer; type depends on table ID
- int nel = tc->getSyscallArg(3); // number of elements
- int lel = tc->getSyscallArg(4); // expected element size
+ int nel = tc->getSyscallArg(3); // number of elements
+ int lel = tc->getSyscallArg(4); // expected element size
switch (id) {
case AlphaTru64::TBL_SYSINFO: {
diff --git a/src/arch/alpha/tru64/tru64.cc b/src/arch/alpha/tru64/tru64.cc
index 56b04846f..c72e975f0 100644
--- a/src/arch/alpha/tru64/tru64.cc
+++ b/src/arch/alpha/tru64/tru64.cc
@@ -33,34 +33,34 @@
// open(2) flags translation table
OpenFlagTransTable AlphaTru64::openFlagTable[] = {
#ifdef _MSC_VER
- { AlphaTru64::TGT_O_RDONLY, _O_RDONLY },
- { AlphaTru64::TGT_O_WRONLY, _O_WRONLY },
- { AlphaTru64::TGT_O_RDWR, _O_RDWR },
- { AlphaTru64::TGT_O_APPEND, _O_APPEND },
- { AlphaTru64::TGT_O_CREAT, _O_CREAT },
- { AlphaTru64::TGT_O_TRUNC, _O_TRUNC },
- { AlphaTru64::TGT_O_EXCL, _O_EXCL },
+ { AlphaTru64::TGT_O_RDONLY, _O_RDONLY },
+ { AlphaTru64::TGT_O_WRONLY, _O_WRONLY },
+ { AlphaTru64::TGT_O_RDWR, _O_RDWR },
+ { AlphaTru64::TGT_O_APPEND, _O_APPEND },
+ { AlphaTru64::TGT_O_CREAT, _O_CREAT },
+ { AlphaTru64::TGT_O_TRUNC, _O_TRUNC },
+ { AlphaTru64::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
- { AlphaTru64::TGT_O_NONBLOCK, _O_NONBLOCK },
+ { AlphaTru64::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
- { AlphaTru64::TGT_O_NOCTTY, _O_NOCTTY },
+ { AlphaTru64::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
- { AlphaTru64::TGT_O_SYNC, _O_SYNC },
+ { AlphaTru64::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
- { AlphaTru64::TGT_O_RDONLY, O_RDONLY },
- { AlphaTru64::TGT_O_WRONLY, O_WRONLY },
- { AlphaTru64::TGT_O_RDWR, O_RDWR },
- { AlphaTru64::TGT_O_APPEND, O_APPEND },
- { AlphaTru64::TGT_O_CREAT, O_CREAT },
- { AlphaTru64::TGT_O_TRUNC, O_TRUNC },
- { AlphaTru64::TGT_O_EXCL, O_EXCL },
- { AlphaTru64::TGT_O_NONBLOCK, O_NONBLOCK },
- { AlphaTru64::TGT_O_NOCTTY, O_NOCTTY },
+ { AlphaTru64::TGT_O_RDONLY, O_RDONLY },
+ { AlphaTru64::TGT_O_WRONLY, O_WRONLY },
+ { AlphaTru64::TGT_O_RDWR, O_RDWR },
+ { AlphaTru64::TGT_O_APPEND, O_APPEND },
+ { AlphaTru64::TGT_O_CREAT, O_CREAT },
+ { AlphaTru64::TGT_O_TRUNC, O_TRUNC },
+ { AlphaTru64::TGT_O_EXCL, O_EXCL },
+ { AlphaTru64::TGT_O_NONBLOCK, O_NONBLOCK },
+ { AlphaTru64::TGT_O_NOCTTY, O_NOCTTY },
#ifdef O_SYNC
- { AlphaTru64::TGT_O_SYNC, O_SYNC },
+ { AlphaTru64::TGT_O_SYNC, O_SYNC },
#endif
#endif /* _MSC_VER */
};
diff --git a/src/arch/alpha/tru64/tru64.hh b/src/arch/alpha/tru64/tru64.hh
index 90e5f12dc..8aa959553 100644
--- a/src/arch/alpha/tru64/tru64.hh
+++ b/src/arch/alpha/tru64/tru64.hh
@@ -46,21 +46,21 @@ class AlphaTru64 : public Tru64
//@{
/// open(2) flag values.
- static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
- static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
- static const int TGT_O_RDWR = 00000002; //!< O_RDWR
- static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
- static const int TGT_O_APPEND = 00000010; //!< O_APPEND
- static const int TGT_O_CREAT = 00001000; //!< O_CREAT
- static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
- static const int TGT_O_EXCL = 00004000; //!< O_EXCL
- static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
- static const int TGT_O_SYNC = 00040000; //!< O_SYNC
- static const int TGT_O_DRD = 00100000; //!< O_DRD
- static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
- static const int TGT_O_CACHE = 00400000; //!< O_CACHE
- static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
- static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
+ static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
+ static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
+ static const int TGT_O_RDWR = 00000002; //!< O_RDWR
+ static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
+ static const int TGT_O_APPEND = 00000010; //!< O_APPEND
+ static const int TGT_O_CREAT = 00001000; //!< O_CREAT
+ static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
+ static const int TGT_O_EXCL = 00004000; //!< O_EXCL
+ static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
+ static const int TGT_O_SYNC = 00040000; //!< O_SYNC
+ static const int TGT_O_DRD = 00100000; //!< O_DRD
+ static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
+ static const int TGT_O_CACHE = 00400000; //!< O_CACHE
+ static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
+ static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
//@}
/// For mmap().
@@ -69,12 +69,12 @@ class AlphaTru64 : public Tru64
//@{
/// For getsysinfo().
static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
- static const unsigned GSI_CPU_INFO = 59; //!< CPU information
- static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
+ static const unsigned GSI_CPU_INFO = 59; //!< CPU information
+ static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine
- static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
- static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
- static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
+ static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
+ static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
+ static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
//@}
//@{