2 files changed, 0 insertions, 17 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 3bc0492b1..bf641d2fe 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -127,18 +127,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-int
-ISA::getInstAsid()
-{
-    return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-ISA::getDataAsid()
-{
-    return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-}
-
 #endif
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index dbd1c43a9..622d1da4c 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -65,11 +65,6 @@ namespace AlphaISA
 
       public:
 
-        // These functions should be removed once the simplescalar cpu
-        // model has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
         MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);