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-rw-r--r--src/arch/alpha/interrupts.hh4
-rw-r--r--src/arch/alpha/isa.cc4
-rw-r--r--src/arch/alpha/isa.hh4
-rw-r--r--src/arch/alpha/kernel_stats.cc8
-rw-r--r--src/arch/alpha/kernel_stats.hh4
-rw-r--r--src/arch/alpha/pagetable.cc4
-rw-r--r--src/arch/alpha/pagetable.hh11
-rw-r--r--src/arch/alpha/process.cc2
-rw-r--r--src/arch/alpha/process.hh2
-rw-r--r--src/arch/alpha/system.cc12
-rw-r--r--src/arch/alpha/system.hh4
-rw-r--r--src/arch/alpha/tlb.cc27
-rw-r--r--src/arch/alpha/tlb.hh11
13 files changed, 49 insertions, 48 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 3e9c90381..1e67f54b5 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -121,14 +121,14 @@ class Interrupts : public SimObject
}
void
- serialize(std::ostream &os)
+ serialize(CheckpointOut &cp) const
{
SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
SERIALIZE_SCALAR(intstatus);
}
void
- unserialize(Checkpoint *cp, const std::string &section)
+ unserialize(CheckpointIn &cp)
{
UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
UNSERIALIZE_SCALAR(intstatus);
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 20f039166..8240037cc 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -53,7 +53,7 @@ ISA::params() const
}
void
-ISA::serialize(std::ostream &os)
+ISA::serialize(CheckpointOut &cp) const
{
SERIALIZE_SCALAR(fpcr);
SERIALIZE_SCALAR(uniq);
@@ -63,7 +63,7 @@ ISA::serialize(std::ostream &os)
}
void
-ISA::unserialize(Checkpoint *cp, const std::string &section)
+ISA::unserialize(CheckpointIn &cp)
{
UNSERIALIZE_SCALAR(fpcr);
UNSERIALIZE_SCALAR(uniq);
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 52e4e98be..6a88ee40b 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -92,8 +92,8 @@ namespace AlphaISA
memset(ipr, 0, sizeof(ipr));
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
int
flattenIntIndex(int reg) const
diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc
index bac5d26cd..94142a031 100644
--- a/src/arch/alpha/kernel_stats.cc
+++ b/src/arch/alpha/kernel_stats.cc
@@ -194,9 +194,9 @@ Statistics::callpal(int code, ThreadContext *tc)
}
void
-Statistics::serialize(ostream &os)
+Statistics::serialize(CheckpointOut &cp) const
{
- ::Kernel::Statistics::serialize(os);
+ ::Kernel::Statistics::serialize(cp);
int exemode = themode;
SERIALIZE_SCALAR(exemode);
SERIALIZE_SCALAR(idleProcess);
@@ -204,9 +204,9 @@ Statistics::serialize(ostream &os)
}
void
-Statistics::unserialize(Checkpoint *cp, const string &section)
+Statistics::unserialize(CheckpointIn &cp)
{
- ::Kernel::Statistics::unserialize(cp, section);
+ ::Kernel::Statistics::unserialize(cp);
int exemode;
UNSERIALIZE_SCALAR(exemode);
UNSERIALIZE_SCALAR(idleProcess);
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
index 837269309..188d3ec4b 100644
--- a/src/arch/alpha/kernel_stats.hh
+++ b/src/arch/alpha/kernel_stats.hh
@@ -86,8 +86,8 @@ class Statistics : public ::Kernel::Statistics
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
};
} // namespace Kernel
diff --git a/src/arch/alpha/pagetable.cc b/src/arch/alpha/pagetable.cc
index 4dff04777..f2b1147f7 100644
--- a/src/arch/alpha/pagetable.cc
+++ b/src/arch/alpha/pagetable.cc
@@ -34,7 +34,7 @@
namespace AlphaISA {
void
-TlbEntry::serialize(std::ostream &os)
+TlbEntry::serialize(CheckpointOut &cp) const
{
SERIALIZE_SCALAR(tag);
SERIALIZE_SCALAR(ppn);
@@ -48,7 +48,7 @@ TlbEntry::serialize(std::ostream &os)
}
void
-TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
+TlbEntry::unserialize(CheckpointIn &cp)
{
UNSERIALIZE_SCALAR(tag);
UNSERIALIZE_SCALAR(ppn);
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index ca44de7fa..0b6524043 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -90,7 +90,7 @@ struct PageTableEntry
};
// ITB/DTB table entry
-struct TlbEntry
+struct TlbEntry : public Serializable
{
Addr tag; // virtual page number tag
Addr ppn; // physical page number
@@ -124,7 +124,10 @@ struct TlbEntry
}
TlbEntry()
- {}
+ : tag(0), ppn(0), xre(0), xwe(0), asn(0),
+ asma(false), fonr(0), fonw(0), valid(0)
+ {
+ }
void
updateVaddr(Addr new_vaddr)
@@ -139,8 +142,8 @@ struct TlbEntry
return ppn << PageShift;
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
};
} // namespace AlphaISA
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index f50131be0..e214c8874 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -175,7 +175,7 @@ AlphaLiveProcess::setupASNReg()
void
-AlphaLiveProcess::loadState(Checkpoint *cp)
+AlphaLiveProcess::loadState(CheckpointIn &cp)
{
LiveProcess::loadState(cp);
// need to set up ASN after unserialization since M5_pid value may
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index d3f9fdfc3..6701017e0 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -42,7 +42,7 @@ class AlphaLiveProcess : public LiveProcess
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void loadState(Checkpoint *cp);
+ void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void initState();
void argsInit(int intSize, int pageSize);
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 3ebc02b64..d2be5492f 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -218,17 +218,17 @@ AlphaSystem::setAlphaAccess(Addr access)
}
void
-AlphaSystem::serializeSymtab(std::ostream &os)
+AlphaSystem::serializeSymtab(CheckpointOut &cp) const
{
- consoleSymtab->serialize("console_symtab", os);
- palSymtab->serialize("pal_symtab", os);
+ consoleSymtab->serialize("console_symtab", cp);
+ palSymtab->serialize("pal_symtab", cp);
}
void
-AlphaSystem::unserializeSymtab(Checkpoint *cp, const std::string &section)
+AlphaSystem::unserializeSymtab(CheckpointIn &cp)
{
- consoleSymtab->unserialize("console_symtab", cp, section);
- palSymtab->unserialize("pal_symtab", cp, section);
+ consoleSymtab->unserialize("console_symtab", cp);
+ palSymtab->unserialize("pal_symtab", cp);
}
AlphaSystem *
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 11a5e90a4..3f4a2367e 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -60,8 +60,8 @@ class AlphaSystem : public System
/**
* Serialization stuff
*/
- virtual void serializeSymtab(std::ostream &os);
- virtual void unserializeSymtab(Checkpoint *cp, const std::string &section);
+ void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
/** Override startup() to provide a path to call setupFuncEvents()
*/
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index a740da388..5f0ed85db 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -30,13 +30,15 @@
* Andrew Schultz
*/
+#include "arch/alpha/tlb.hh"
+
+#include <algorithm>
#include <memory>
#include <string>
#include <vector>
#include "arch/alpha/faults.hh"
#include "arch/alpha/pagetable.hh"
-#include "arch/alpha/tlb.hh"
#include "arch/generic/debugfaults.hh"
#include "base/inifile.hh"
#include "base/str.hh"
@@ -62,17 +64,13 @@ bool uncacheBit40 = false;
#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), nlu(0)
+ : BaseTLB(p), table(p->size), nlu(0)
{
- table = new TlbEntry[size];
- memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
}
TLB::~TLB()
{
- if (table)
- delete [] table;
}
void
@@ -283,7 +281,7 @@ void
TLB::flushAll()
{
DPRINTF(TLB, "flushAll\n");
- memset(table, 0, sizeof(TlbEntry) * size);
+ std::fill(table.begin(), table.end(), TlbEntry());
flushCache();
lookupTable.clear();
nlu = 0;
@@ -345,25 +343,26 @@ TLB::flushAddr(Addr addr, uint8_t asn)
void
-TLB::serialize(ostream &os)
+TLB::serialize(CheckpointOut &cp) const
{
+ const unsigned size(table.size());
SERIALIZE_SCALAR(size);
SERIALIZE_SCALAR(nlu);
- for (int i = 0; i < size; i++) {
- nameOut(os, csprintf("%s.Entry%d", name(), i));
- table[i].serialize(os);
- }
+ for (int i = 0; i < size; i++)
+ table[i].serializeSection(cp, csprintf("Entry%d", i));
}
void
-TLB::unserialize(Checkpoint *cp, const string &section)
+TLB::unserialize(CheckpointIn &cp)
{
+ unsigned size(0);
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu);
+ table.resize(size);
for (int i = 0; i < size; i++) {
- table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
+ table[i].unserializeSection(cp, csprintf("Entry%d", i));
if (table[i].valid) {
lookupTable.insert(make_pair(table[i].tag, i));
}
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index ccd4362d3..73ffda1f6 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -74,11 +74,10 @@ class TLB : public BaseTLB
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
- TlbEntry *table; // the Page Table
- int size; // TLB Size
+ std::vector<TlbEntry> table; // the Page Table
int nlu; // not last used entry (for replacement)
- void nextnlu() { if (++nlu >= size) nlu = 0; }
+ void nextnlu() { if (++nlu >= table.size()) nlu = 0; }
TlbEntry *lookup(Addr vpn, uint8_t asn);
public:
@@ -90,7 +89,7 @@ class TLB : public BaseTLB
virtual void regStats();
- int getsize() const { return size; }
+ int getsize() const { return table.size(); }
TlbEntry &index(bool advance = true);
void insert(Addr vaddr, TlbEntry &entry);
@@ -118,8 +117,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
// Most recently used page table entries
TlbEntry *EntryCache[3];
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 06:18:47 +0000