summaryrefslogtreecommitdiff
path: root/src/arch/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/ev5.cc14
-rw-r--r--src/arch/alpha/floatregfile.hh4
-rw-r--r--src/arch/alpha/intregfile.hh4
-rw-r--r--src/arch/alpha/isa/fp.isa12
4 files changed, 17 insertions, 17 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ec5090eb8..86b8fd2d0 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
- retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
- retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
- retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
- retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
- retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
- retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
- retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
+ retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
+ retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
+ retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
+ retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
+ retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
+ retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
+ retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
}
break;
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index d289f5785..0c5fe17a7 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -35,7 +35,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/types.hh"
-#include <string.h>
+#include <cstring>
#include <iostream>
class Checkpoint;
@@ -61,7 +61,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
- { bzero(d, sizeof(d)); }
+ { std::memset(d, 0, sizeof(d)); }
};
}
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 0d65f69e0..dea160992 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -35,7 +35,7 @@
#include "arch/alpha/types.hh"
#include <iostream>
-#include <strings.h>
+#include <cstring>
class Checkpoint;
@@ -71,7 +71,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
- { bzero(regs, sizeof(regs)); }
+ { std::memset(regs, 0, sizeof(regs)); }
};
}
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index a350aa05f..773e7d10c 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -192,10 +192,10 @@ output decoder {{
}
const int AlphaFP::alphaToC99RoundingMode[] = {
- FE_TOWARDZERO, // Chopped
- FE_DOWNWARD, // Minus_Infinity
- FE_TONEAREST, // Normal
- FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
+ M5_FE_TOWARDZERO, // Chopped
+ M5_FE_DOWNWARD, // Minus_Infinity
+ M5_FE_TONEAREST, // Normal
+ M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@@ -228,10 +228,10 @@ def template FloatingPointExecute {{
if (roundingMode == Normal) {
%(code)s;
} else {
- fesetround(getC99RoundingMode(
+ m5_fesetround(getC99RoundingMode(
xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
%(code)s;
- fesetround(FE_TONEAREST);
+ m5_fesetround(M5_FE_TONEAREST);
}
#else
if (roundingMode != Normal && !warnedOnRounding) {