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-rw-r--r--src/arch/alpha/ev5.cc50
-rw-r--r--src/arch/alpha/isa/decoder.isa34
-rw-r--r--src/arch/alpha/isa/main.isa3
3 files changed, 52 insertions, 35 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index c11b3632e..7dc02a611 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -547,3 +547,53 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
}
} // namespace AlphaISA
+
+#if FULL_SYSTEM
+
+using namespace AlphaISA;
+
+Fault
+SimpleThread::hwrei()
+{
+ if (!(readPC() & 0x3))
+ return new UnimplementedOpcodeFault;
+
+ setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
+
+ if (!misspeculating()) {
+ if (kernelStats)
+ kernelStats->hwrei();
+ }
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
+}
+
+/**
+ * Check for special simulator handling of specific PAL calls.
+ * If return value is false, actual PAL call will be suppressed.
+ */
+bool
+SimpleThread::simPalCheck(int palFunc)
+{
+ if (kernelStats)
+ kernelStats->callpal(palFunc, tc);
+
+ switch (palFunc) {
+ case PAL::halt:
+ halt();
+ if (--System::numSystemsRunning == 0)
+ exitSimLoop("all cpus halted");
+ break;
+
+ case PAL::bpt:
+ case PAL::bugchk:
+ if (system->breakpoint())
+ return false;
+ break;
+ }
+
+ return true;
+}
+
+#endif // FULL_SYSTEM
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 06676ae87..270940df2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -698,28 +698,7 @@ decode OPCODE default Unknown::unknown() {
else {
// check to see if simulator wants to do something special
// on this PAL call (including maybe suppress it)
-
- bool dopal = true;
-
- ThreadContext * tc = xc->tcBase();
- AlphaISA::Kernel::Statistics * kernelStats = tc->getKernelStats();
- System * system = tc->getSystemPtr();
- if (kernelStats)
- kernelStats->callpal(palFunc, tc);
-
- switch (palFunc) {
- case PAL::halt:
- tc->halt();
- if (--System::numSystemsRunning == 0)
- exitSimLoop("all cpus halted");
- break;
-
- case PAL::bpt:
- case PAL::bugchk:
- if (system->breakpoint())
- dopal = false;
- break;
- }
+ bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
xc->setMiscReg(IPR_EXC_ADDR, NPC);
@@ -807,16 +786,7 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1: hw_rei({{
- NPC = ExcAddr;
- ThreadContext * tc = xc->tcBase();
- if (!tc->misspeculating()) {
- AlphaISA::Kernel::Statistics * kernelStats =
- tc->getKernelStats();
- if (kernelStats)
- kernelStats->hwrei();
- }
- }}, IsSerializing, IsSerializeBefore);
+ 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 0f7f74359..5231712c8 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -69,8 +69,6 @@ output exec {{
#include <math.h>
#if FULL_SYSTEM
-#include "arch/alpha/kernel_stats.hh"
-#include "arch/alpha/osfpal.hh"
#include "sim/pseudo_inst.hh"
#endif
#include "arch/alpha/ipr.hh"
@@ -189,7 +187,6 @@ def operands {{
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
- 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),