diff options
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 16 | ||||
| -rw-r--r-- | src/arch/alpha/isa/mem.isa | 9 |
2 files changed, 7 insertions, 18 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index e2947cf4a..937b38fce 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -47,11 +47,6 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ Fa = Mem.df; }}); 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC); 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC); -#ifdef USE_COPY - 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, - {{ fault = xc->copySrcTranslate(EA); }}, - inst_flags = [IsMemRef, IsLoad, IsCopy]); -#endif } format LoadOrPrefetch { @@ -71,11 +66,6 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ Mem.df = Fa; }}); -#ifdef USE_COPY - 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, - {{ fault = xc->copy(EA); }}, - inst_flags = [IsMemRef, IsStore, IsCopy]); -#endif } format StoreCond { @@ -788,10 +778,8 @@ decode OPCODE default Unknown::unknown() { format MiscPrefetch { 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, - {{ xc->writeHint(EA, 64, memAccessFlags); }}, - mem_flags = PREFETCH, - inst_flags = [IsMemRef, IsDataPrefetch, - IsStore, MemWriteOp]); + {{ ; }}, + mem_flags = PREFETCH); } format BasicOperate { diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index 799f910c3..862fe0878 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -396,6 +396,7 @@ def template MiscExecute {{ %(op_rd)s; %(ea_code)s; + warn_once("Prefetch instrutions is Alpha do not do anything\n"); if (fault == NoFault) { %(memacc_code)s; } @@ -404,6 +405,8 @@ def template MiscExecute {{ } }}; +// Prefetches in Alpha don't actually do anything +// They just build an effective address and complete def template MiscInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -530,12 +533,10 @@ def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, inst_flags = makeList(inst_flags) pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] - pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', - 'IsDataPrefetch', 'MemReadOp'] + pf_inst_flags = inst_flags (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ - LoadStoreBase(name, Name + 'Prefetch', ea_code, - 'xc->prefetch(EA, memAccessFlags);', + LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') header_output += pf_header_output |