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-rw-r--r--src/arch/alpha/ev5.cc17
-rw-r--r--src/arch/alpha/isa/decoder.isa11
-rw-r--r--src/arch/alpha/isa/main.isa2
3 files changed, 12 insertions, 18 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 7dc02a611..eefe86bff 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -552,23 +552,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
using namespace AlphaISA;
-Fault
-SimpleThread::hwrei()
-{
- if (!(readPC() & 0x3))
- return new UnimplementedOpcodeFault;
-
- setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
-
- if (!misspeculating()) {
- if (kernelStats)
- kernelStats->hwrei();
- }
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
/**
* Check for special simulator handling of specific PAL calls.
* If return value is false, actual PAL call will be suppressed.
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 270940df2..8025ba69f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -786,7 +786,16 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+ 1: hw_rei({{
+ NPC = ExcAddr;
+ ThreadContext * tc = xc->tcBase();
+ if (!tc->misspeculating()) {
+ AlphaISA::Kernel::Statistics * kernelStats =
+ tc->getKernelStats();
+ if (kernelStats)
+ kernelStats->hwrei();
+ }
+ }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 5231712c8..078982697 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -69,6 +69,7 @@ output exec {{
#include <math.h>
#if FULL_SYSTEM
+#include "arch/alpha/kernel_stats.hh"
#include "sim/pseudo_inst.hh"
#endif
#include "arch/alpha/ipr.hh"
@@ -187,6 +188,7 @@ def operands {{
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
+ 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),