diff options
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 11 | ||||
| -rw-r--r-- | src/arch/alpha/utility.hh | 7 |
2 files changed, 0 insertions, 18 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 676d7a713..29910caa6 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -80,17 +80,6 @@ initCPU(ThreadContext *tc, int cpuId) delete reset; } -template <class CPU> -void -zeroRegisters(CPU *cpu) -{ - // Insure ISA semantics - // (no longer very clean due to the change in setIntReg() in the - // cpu model. Consider changing later.) - cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0); -} - //////////////////////////////////////////////////////////////////////// // // diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index bf585fdab..46af1217e 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -58,13 +58,6 @@ inUserMode(ThreadContext *tc) return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; } -/** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template <class TC> -void zeroRegisters(TC *tc); - // Alpha IPR register accessors inline bool PcPAL(Addr addr) { return addr & 0x3; } inline void startupCPU(ThreadContext *tc, int cpuId) |