4 files changed, 125 insertions, 9 deletions

diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index d5f9eec0f..a5a3a7861 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -42,6 +42,13 @@ class Checkpoint;
 
 namespace AlphaISA {
 
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
 class FloatRegFile
 {
   public:
@@ -54,6 +61,55 @@ class FloatRegFile
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+
+    FloatReg
+    readReg(int floatReg)
+    {
+        return d[floatReg];
+    }
+
+    FloatReg
+    readReg(int floatReg, int width)
+    {
+        return readReg(floatReg);
+    }
+
+    FloatRegBits
+    readRegBits(int floatReg)
+    {
+        return q[floatReg];
+    }
+
+    FloatRegBits
+    readRegBits(int floatReg, int width)
+    {
+        return readRegBits(floatReg);
+    }
+
+    void
+    setReg(int floatReg, const FloatReg &val)
+    {
+        d[floatReg] = val;
+    }
+
+    void
+    setReg(int floatReg, const FloatReg &val, int width)
+    {
+        setReg(floatReg, val);
+    }
+
+    void
+    setRegBits(int floatReg, const FloatRegBits &val)
+    {
+        q[floatReg] = val;
+    }
+
+    void
+    setRegBits(int floatReg, const FloatRegBits &val, int width)
+    {
+        setRegBits(floatReg, val);
+    }
+
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index cd5e117ec..9a8503637 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -65,6 +65,8 @@ output header {{
 
         const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
         const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+        Request::Flags memAccFlags() { return memAccessFlags; }
     };
 
     /**
@@ -176,6 +178,8 @@ def template LoadStoreDeclare {{
         %(InitiateAccDeclare)s
 
         %(CompleteAccDeclare)s
+
+        %(MemAccSizeDeclare)s
     };
 }};
 
@@ -190,6 +194,25 @@ def template CompleteAccDeclare {{
                       Trace::InstRecord *) const;
 }};
 
+def template MemAccSizeDeclare {{
+    int memAccSize(%(CPU_exec_context)s *xc);
+}};
+
+def template MiscMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        panic("Misc instruction does not support split access method!");
+        return 0;
+    }
+}};
+
+def template LoadStoreMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        // Return the memory access size in bytes
+        return (%(mem_acc_size)d / 8);
+    }
+}};
 
 def template EACompConstructor {{
     /** TODO: change op_class to AddrGenOp or something (requires
@@ -620,6 +643,14 @@ def template MiscCompleteAcc {{
     }
 }};
 
+def template MiscMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        panic("Misc instruction does not support split access method!");
+        return 0;
+    }
+}};
+
 // load instructions use Ra as dest, so check for
 // Ra == 31 to detect nops
 def template LoadNopCheckDecode {{
@@ -693,6 +724,11 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
 
+    if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+      memAccSizeTemplate = eval('LoadStoreMemAccSize')
+    else:
+      memAccSizeTemplate = eval('MiscMemAccSize')
+
     # (header_output, decoder_output, decode_block, exec_output)
     return (LoadStoreDeclare.subst(iop),
             EACompConstructor.subst(ea_iop)
@@ -703,7 +739,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
             + memAccExecTemplate.subst(memacc_iop)
             + fullExecTemplate.subst(iop)
             + initiateAccTemplate.subst(iop)
-            + completeAccTemplate.subst(iop))
+            + completeAccTemplate.subst(iop)
+            + memAccSizeTemplate.subst(memacc_iop))
 }};
 
 def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 61a86f1fb..5dc316a83 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+    cpu = _cpu;
+    initializeIprTable();
+}
+
+
 MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_reg)
 }
 
 MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
@@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
 }
 
 void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
@@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
 }
 
 void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+                    unsigned tid)
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 6105ce683..b194e00bb 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -41,6 +41,7 @@
 
 class Checkpoint;
 class ThreadContext;
+class BaseCPU;
 
 namespace AlphaISA {
 
@@ -68,6 +69,8 @@ class MiscRegFile
 
     InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
+    BaseCPU *cpu;
+
   protected:
     InternalProcReg readIpr(int idx, ThreadContext *tc);
     void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
@@ -78,16 +81,18 @@ class MiscRegFile
         initializeIprTable();
     }
 
+    MiscRegFile(BaseCPU *cpu);
+
     // These functions should be removed once the simplescalar cpu
     // model has been replaced.
     int getInstAsid();
     int getDataAsid();
 
-    MiscReg readRegNoEffect(int misc_reg);
-    MiscReg readReg(int misc_reg, ThreadContext *tc);
+    MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+    MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
 
-    void setRegNoEffect(int misc_reg, const MiscReg &val);
-    void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+    void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+    void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned tid = 0);
 
     void
     clear()
@@ -101,6 +106,16 @@ class MiscRegFile
 
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
+
+    void reset(std::string core_name, unsigned num_threads,
+               unsigned num_vpes, BaseCPU *_cpu)
+    { }
+
+
+    void expandForMultithreading(unsigned num_threads, unsigned num_vpes)
+    { }
+
+
 };
 
 void copyIprs(ThreadContext *src, ThreadContext *dest);