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-rw-r--r--src/arch/arm/ArmISA.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index eaec92f4d..f5c56cfd5 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -40,6 +40,8 @@ from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
+from ArmPMU import ArmPMU
+
class ArmISA(SimObject):
type = 'ArmISA'
cxx_class = 'ArmISA::ISA'
@@ -47,6 +49,8 @@ class ArmISA(SimObject):
system = Param.System(Parent.any, "System this ISA object belongs to")
+ pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
+
midr = Param.UInt32(0x410fc0f0, "MIDR value")
# See section B4.1.93 - B4.1.94 of the ARM ARM