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Diffstat (limited to 'src/arch/arm/ArmTLB.py')
| -rw-r--r-- | src/arch/arm/ArmTLB.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4e6c69f72..b3f711d83 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -63,6 +63,7 @@ class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' cxx_header = "arch/arm/tlb.hh" + sys = Param.System(Parent.any, "system object parameter") size = Param.Int(64, "TLB size") walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?") |