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Diffstat (limited to 'src/arch/arm/ArmTLB.py')
| -rw-r--r-- | src/arch/arm/ArmTLB.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 0a931b7e5..c70dd80c8 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -45,6 +45,7 @@ from MemObject import MemObject class ArmTableWalker(MemObject): type = 'ArmTableWalker' cxx_class = 'ArmISA::TableWalker' + cxx_header = "arch/arm/table_walker.hh" port = MasterPort("Port for TableWalker to do walk the translation with") sys = Param.System(Parent.any, "system object parameter") num_squash_per_cycle = Param.Unsigned(2, @@ -53,5 +54,6 @@ class ArmTableWalker(MemObject): class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' + cxx_header = "arch/arm/tlb.hh" size = Param.Int(64, "TLB size") walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") |