diff options
Diffstat (limited to 'src/arch/arm/ArmTLB.py')
-rw-r--r-- | src/arch/arm/ArmTLB.py | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 01ac8016a..4e6c69f72 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -1,6 +1,6 @@ # -*- mode:python -*- -# Copyright (c) 2009, 2013 ARM Limited +# Copyright (c) 2009, 2013, 2015 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -48,11 +48,17 @@ class ArmTableWalker(MemObject): cxx_class = 'ArmISA::TableWalker' cxx_header = "arch/arm/table_walker.hh" is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?") - port = MasterPort("Port for TableWalker to do walk the translation with") - sys = Param.System(Parent.any, "system object parameter") num_squash_per_cycle = Param.Unsigned(2, "Number of outstanding walks that can be squashed per cycle") + # The port to the memory system. This port is ultimately belonging + # to the Stage2MMU, and shared by the two table walkers, but we + # access it through the ITB and DTB walked objects in the CPU for + # symmetry with the other ISAs. + port = MasterPort("Port used by the two table walkers") + + sys = Param.System(Parent.any, "system object parameter") + class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' @@ -77,10 +83,16 @@ class ArmStage2MMU(SimObject): tlb = Param.ArmTLB("Stage 1 TLB") stage2_tlb = Param.ArmTLB("Stage 2 TLB") + sys = Param.System(Parent.any, "system object parameter") + class ArmStage2IMMU(ArmStage2MMU): + # We rely on the itb being a parameter of the CPU, and get the + # appropriate object that way tlb = Parent.itb - stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker()) + stage2_tlb = ArmStage2TLB() class ArmStage2DMMU(ArmStage2MMU): + # We rely on the dtb being a parameter of the CPU, and get the + # appropriate object that way tlb = Parent.dtb - stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker()) + stage2_tlb = ArmStage2TLB() |