1 files changed, 54 insertions, 0 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
new file mode 100644
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+++ b/src/arch/arm/ArmTLB.py
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+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Florida State University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Stephen Hines
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class ArmTLB(SimObject):
+    abstract = True
+    type = 'ArmTLB'
+    cxx_class = 'ArmISA::TLB'
+    size = Param.Int("TLB size")
+
+class ArmDTB(ArmTLB):
+    type = 'ArmDTB'
+    cxx_class = 'ArmISA::DTB'
+    size = 64
+
+class ArmITB(ArmTLB):
+    type = 'ArmITB'
+    cxx_class = 'ArmISA::ITB'
+    size = 64
+
+class ArmUTB(ArmTLB):
+    type = 'ArmUTB'
+    cxx_class = 'ArmISA::UTB'
+    size = 64
+