1 files changed, 13 insertions, 16 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index a907e52fb..171c04718 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -54,35 +54,32 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
     Source('miscregs.cc')
-    Source('predecoder.cc')
     Source('nativetrace.cc')
+    Source('predecoder.cc')
+    Source('process.cc')
+    Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
+    Source('table_walker.cc')
     Source('tlb.cc')
     Source('utility.cc')
-    Source('remote_gdb.cc')
+    Source('vtophys.cc')
 
+    SimObject('ArmInterrupts.py')
     SimObject('ArmNativeTrace.py')
+    SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
 
     DebugFlag('Arm')
     DebugFlag('TLBVerbose')
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('Predecoder', "Instructions returned by the predecoder")
-    if env['FULL_SYSTEM']:
-        Source('interrupts.cc')
-        Source('stacktrace.cc')
-        Source('system.cc')
-        Source('vtophys.cc')
-        Source('linux/system.cc')
-        Source('table_walker.cc')
-        
-        SimObject('ArmInterrupts.py')
-        SimObject('ArmSystem.py')
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')