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-rw-r--r--src/arch/arm/SConscript2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 73fcc730b..67997f4e0 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -65,12 +65,14 @@ if env['TARGET_ISA'] == 'arm':
SimObject('ArmTLB.py')
TraceFlag('Arm')
+ TraceFlag('TLBVerbose')
TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
TraceFlag('Predecoder', "Instructions returned by the predecoder")
if env['FULL_SYSTEM']:
Source('interrupts.cc')
Source('stacktrace.cc')
Source('system.cc')
+ Source('table_walker.cc')
SimObject('ArmInterrupts.py')
SimObject('ArmSystem.py')