diff options
Diffstat (limited to 'src/arch/arm/fastmodel/CortexA76/thread_context.cc')
| -rw-r--r-- | src/arch/arm/fastmodel/CortexA76/thread_context.cc | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index c7c92d158..281c70aca 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -93,9 +93,51 @@ CortexA76TC::initFromIrisInstance(const ResourceMap &resources) extractResourceMap(intReg32Ids, resources, intReg32IdxNameMap); extractResourceMap(intReg64Ids, resources, intReg64IdxNameMap); + extractResourceMap(ccRegIds, resources, ccRegIdxNameMap); + extractResourceMap(vecRegIds, resources, vecRegIdxNameMap); } +RegVal +CortexA76TC::readCCRegFlat(RegIndex idx) const +{ + RegVal result = Iris::ThreadContext::readCCRegFlat(idx); + switch (idx) { + case ArmISA::CCREG_NZ: + result = ((CPSR)result).nz; + break; + case ArmISA::CCREG_FP: + result = bits(result, 31, 28); + break; + default: + break; + } + return result; +} + +void +CortexA76TC::setCCRegFlat(RegIndex idx, RegVal val) +{ + switch (idx) { + case ArmISA::CCREG_NZ: + { + CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); + cpsr.nz = val; + val = cpsr; + } + break; + case ArmISA::CCREG_FP: + { + FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR); + val = insertBits(fpscr, 31, 28, val); + } + break; + default: + break; + } + Iris::ThreadContext::setCCRegFlat(idx, val); +} + iris::MemorySpaceId CortexA76TC::getBpSpaceId(Addr pc) const { @@ -798,6 +840,14 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::intReg64IdxNameMap({ { ArmISA::INTREG_SPX, "SP" }, }); +Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({ + { ArmISA::CCREG_NZ, "CPSR" }, + { ArmISA::CCREG_C, "CPSR.C" }, + { ArmISA::CCREG_V, "CPSR.V" }, + { ArmISA::CCREG_GE, "CPSR.GE" }, + { ArmISA::CCREG_FP, "FPSCR" }, +}); + Iris::ThreadContext::IdxNameMap CortexA76TC::vecRegIdxNameMap({ { 0, "V0" }, { 1, "V1" }, { 2, "V2" }, { 3, "V3" }, { 4, "V4" }, { 5, "V5" }, { 6, "V6" }, { 7, "V7" }, |