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Diffstat (limited to 'src/arch/arm/fastmodel/arm/cpu.cc')
-rw-r--r-- | src/arch/arm/fastmodel/arm/cpu.cc | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/arm/cpu.cc b/src/arch/arm/fastmodel/arm/cpu.cc new file mode 100644 index 000000000..47420368f --- /dev/null +++ b/src/arch/arm/fastmodel/arm/cpu.cc @@ -0,0 +1,65 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/arm/fastmodel/arm/cpu.hh" + +#include "scx/scx_iris.h" + +namespace FastModel +{ + +ArmCPU::ArmCPU(FastModelArmCPUParams *params) : + Iris::ArmCPU(params, scx::scx_get_iris_connection_interface()), + mem(name() + ".mem", this) +{ +} + +void +ArmCPU::initState() +{ + auto cntfrq = static_cast<const FastModelArmCPUParams *>(params())->cntfrq; + for (auto *tc : threadContexts) + tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, cntfrq); +} + +Port & +ArmCPU::getPort(const std::string &if_name, PortID idx) +{ + if (if_name == "mem") + return mem; + return Iris::ArmCPU::getPort(if_name, idx); +} + +} // namespace FastModel + +FastModel::ArmCPU * +FastModelArmCPUParams::create() +{ + return new FastModel::ArmCPU(this); +} |