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Diffstat (limited to 'src/arch/arm/fastmodel/iris/Iris.py')
-rw-r--r-- | src/arch/arm/fastmodel/iris/Iris.py | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py new file mode 100644 index 000000000..781a146ad --- /dev/null +++ b/src/arch/arm/fastmodel/iris/Iris.py @@ -0,0 +1,55 @@ +# Copyright 2019 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * + +from m5.objects.BaseCPU import BaseCPU + +class IrisBaseCPU(BaseCPU): + type = 'IrisBaseCPU' + abstract = True + cxx_class = 'Iris::BaseCPU' + cxx_header = 'arch/arm/fastmodel/iris/cpu.hh' + + @classmethod + def memory_mode(cls): + return 'atomic_noncaching' + + @classmethod + def require_caches(cls): + return False + + @classmethod + def support_take_over(cls): + #TODO Make this work. + return False + + evs = Param.SystemC_ScModule(Parent.any, + "Fast model exported virtual subsystem holding cores") + core_paths = VectorParam.String( + "Sub-paths to elements in the EVS which are cores") |