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-rw-r--r--src/arch/arm/fastmodel/iris/cpu.hh12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index c6c75a2ff..f7be5cb76 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -49,6 +49,9 @@ static const std::string PeriodAttributeName = "gem5_clock_period_attribute";
// The name of the attribute the subsystem should create which will be set to
// a pointer to its corresponding gem5 CPU.
static const std::string Gem5CpuAttributeName = "gem5_cpu";
+// The name of the attribute the subsystem should create to hold the
+// sendFunctional delegate for port proxies.
+static const std::string SendFunctionalAttributeName = "gem5_send_functional";
// This CPU class adds some mechanisms which help attach the gem5 and fast
// model CPUs to each other. It acts as a base class for the gem5 CPU, and
@@ -83,12 +86,21 @@ class BaseCPU : public ::BaseCPU
Counter totalInsts() const override;
Counter totalOps() const override { return totalInsts(); }
+ PortProxy::SendFunctionalFunc
+ getSendFunctional() override
+ {
+ if (sendFunctional)
+ return sendFunctional->value;
+ return ::BaseCPU::getSendFunctional();
+ }
+
protected:
sc_core::sc_module *evs;
private:
sc_core::sc_event *clockEvent;
sc_core::sc_attribute<Tick> *periodAttribute;
+ sc_core::sc_attribute<PortProxy::SendFunctionalFunc> *sendFunctional;
protected:
void