1 files changed, 20 insertions, 10 deletions

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 68c5fa0e8..061392f59 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -47,6 +47,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Faults.hh"
+#include "sim/full_system.hh"
 
 namespace ArmISA
 {
@@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc)
 
 }
 
-#if FULL_SYSTEM
-
 void 
 ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // ARM ARM B1.6.3
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     countStat()++;
 
     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
@@ -165,16 +166,21 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    tc->getCpuPtr()->clearInterrupts();
-    tc->clearArchRegs();
+    if (FullSystem) {
+        tc->getCpuPtr()->clearInterrupts();
+        tc->clearArchRegs();
+    }
     ArmFault::invoke(tc, inst);
 }
 
-#else
-
 void
 UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        ArmFault::invoke(tc, inst);
+        return;
+    }
+
     // If the mnemonic isn't defined this has to be an unknown instruction.
     assert(unknown || mnemonic != NULL);
     if (disabled) {
@@ -192,6 +198,11 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        ArmFault::invoke(tc, inst);
+        return;
+    }
+
     // As of now, there isn't a 32 bit thumb version of this instruction.
     assert(!machInst.bigThumb);
     uint32_t callNum;
@@ -205,8 +216,6 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
     tc->pcState(pc);
 }
 
-#endif // FULL_SYSTEM
-
 template<class T>
 void
 AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
@@ -245,13 +254,14 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
 void
 ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
     DPRINTF(Faults, "Invoking ArmSev Fault\n");
-#if FULL_SYSTEM
+    if (!FullSystem)
+        return;
+
     // Set sev_mailbox to 1, clear the pending interrupt from remote
     // SEV execution and let pipeline continue as pcState is still
     // valid.
     tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
     tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
-#endif
 }
 
 // return via SUBS pc, lr, xxx; rfe, movs, ldm