diff options
Diffstat (limited to 'src/arch/arm/insts/branch64.hh')
| -rw-r--r-- | src/arch/arm/insts/branch64.hh | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh index 48881e0c2..731c1869c 100644 --- a/src/arch/arm/insts/branch64.hh +++ b/src/arch/arm/insts/branch64.hh @@ -55,12 +55,14 @@ class BranchImm64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Conditionally Branch to a target computed with an immediate @@ -75,7 +77,8 @@ class BranchImmCond64 : public BranchImm64 BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with a register @@ -90,7 +93,8 @@ class BranchReg64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Ret instruction @@ -102,7 +106,8 @@ class BranchRet64 : public BranchReg64 BranchReg64(mnem, _machInst, __opClass, _op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Eret instruction @@ -113,7 +118,8 @@ class BranchEret64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with an immediate and a register @@ -129,12 +135,14 @@ class BranchImmReg64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with two immediates @@ -153,12 +161,14 @@ class BranchImmImmReg64 : public ArmStaticInst imm1(_imm1), imm2(_imm2), op1(_op1) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; } |