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-rw-r--r--src/arch/arm/insts/misc64.cc22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 423aaca25..cf625ebef 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -35,6 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
+ * Giacomo Travaglini
*/
#include "arch/arm/insts/misc64.hh"
@@ -321,6 +322,27 @@ MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
return trap_to_mon;
}
+RegVal
+MiscRegImmOp64::miscRegImm() const
+{
+ if (dest == MISCREG_SPSEL) {
+ return imm & 0x1;
+ } else {
+ panic("Not a valid PSTATE field register\n");
+ }
+}
+
+std::string
+MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printMiscReg(ss, dest);
+ ss << ", ";
+ ccprintf(ss, "#0x%x", imm);
+ return ss.str();
+}
+
std::string
MiscRegRegImmOp64::generateDisassembly(
Addr pc, const SymbolTable *symtab) const