diff options
Diffstat (limited to 'src/arch/arm/insts/pred_inst.cc')
| -rw-r--r-- | src/arch/arm/insts/pred_inst.cc | 49 |
1 files changed, 47 insertions, 2 deletions
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc index b1b21677c..94386e400 100644 --- a/src/arch/arm/insts/pred_inst.cc +++ b/src/arch/arm/insts/pred_inst.cc @@ -48,7 +48,16 @@ std::string PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - printDataInst(ss, false); + unsigned rotate = machInst.rotate * 2; + uint32_t imm = machInst.imm; + imm = (imm << (32 - rotate)) | (imm >> rotate); + printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField, + (IntRegIndex)(uint32_t)machInst.rd, + (IntRegIndex)(uint32_t)machInst.rn, + (IntRegIndex)(uint32_t)machInst.rm, + (IntRegIndex)(uint32_t)machInst.rs, + machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, + imm); return ss.str(); } @@ -56,7 +65,43 @@ std::string PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - printDataInst(ss, true); + unsigned rotate = machInst.rotate * 2; + uint32_t imm = machInst.imm; + imm = (imm << (32 - rotate)) | (imm >> rotate); + printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField, + (IntRegIndex)(uint32_t)machInst.rd, + (IntRegIndex)(uint32_t)machInst.rn, + (IntRegIndex)(uint32_t)machInst.rm, + (IntRegIndex)(uint32_t)machInst.rs, + machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, + imm); + return ss.str(); +} + +std::string +DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, + INTREG_ZERO, INTREG_ZERO, 0, LSL, imm); + return ss.str(); +} + +std::string +DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, + op2, INTREG_ZERO, shiftAmt, shiftType, 0); + return ss.str(); +} + +std::string +DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1, + op2, shift, 0, shiftType, 0); return ss.str(); } |