2 files changed, 61 insertions, 3 deletions

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa9e..b40de0229 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 
 std::string
 RegRegRegImmOp64::generateDisassembly(
-        Addr pc, const SymbolTable *symtab) const
+    Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@ UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+    Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printMiscReg(ss, dest);
+    ss << ", ";
+    printIntReg(ss, op1);
+    return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+    Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printIntReg(ss, dest);
+    ss << ", ";
+    printMiscReg(ss, op1);
+    return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e18224..384d94628 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@ class UnknownOp64 : public ArmStaticInst
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+    MiscRegIndex dest;
+    IntRegIndex op1;
+    uint32_t imm;
+
+    MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+                      OpClass __opClass, MiscRegIndex _dest,
+                      IntRegIndex _op1, uint32_t _imm) :
+        ArmStaticInst(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+    IntRegIndex dest;
+    MiscRegIndex op1;
+    uint32_t imm;
+
+    RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+                      OpClass __opClass, IntRegIndex _dest,
+                      MiscRegIndex _op1, uint32_t _imm) :
+        ArmStaticInst(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 #endif