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-rw-r--r--src/arch/arm/insts/misc.cc10
-rw-r--r--src/arch/arm/insts/misc.hh14
2 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index a5a4e3b32..0eae37de0 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -153,6 +153,16 @@ ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 53281400e..6d78b311a 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -107,6 +107,20 @@ class ImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ uint64_t imm;
+
+ RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, uint64_t _imm) :
+ PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegRegOp : public PredOp
{
protected: