summaryrefslogtreecommitdiff
path: root/src/arch/arm/insts
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/mem64.cc5
-rw-r--r--src/arch/arm/insts/misc.cc12
-rw-r--r--src/arch/arm/insts/misc.hh19
3 files changed, 4 insertions, 32 deletions
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0aee63f2c..fa8fdf0af 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -53,9 +53,8 @@ SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
- ccprintf(ss, ", [");
+ ccprintf(ss, ", ");
printIntReg(ss, base);
- ccprintf(ss, "]");
return ss.str();
}
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index ba97eff09..9c7a051f5 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -322,16 +322,6 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
-MiscRegRegImmMemOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
-{
- std::stringstream ss;
- printMnemonic(ss);
- printIntReg(ss, op1);
- return ss.str();
-}
-
-std::string
UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst %#08x)", "unknown", machInst);
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 72d1694c9..5c387a500 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -344,23 +344,6 @@ class RegImmRegShiftOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-class MiscRegRegImmMemOp : public PredOp
-{
- protected:
- MiscRegIndex dest;
- IntRegIndex op1;
- uint64_t imm;
-
- MiscRegRegImmMemOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, MiscRegIndex _dest, IntRegIndex _op1,
- uint64_t _imm) :
- PredOp(mnem, _machInst, __opClass),
- dest(_dest), op1(_op1), imm(_imm)
- {}
-
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
class UnknownOp : public PredOp
{
protected: