2 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index a63bad690..87d3d1796 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -144,6 +144,15 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 }
 
 std::string
+ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    ccprintf(ss, "#%d", imm);
+    return ss.str();
+}
+
+std::string
 RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 23f777c2d..8080c4e1f 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -94,6 +94,19 @@ class MsrRegOp : public MsrBase
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class ImmOp : public PredOp
+{
+  protected:
+    uint32_t imm;
+
+    ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+             uint32_t _imm) :
+        PredOp(mnem, _machInst, __opClass), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegRegOp : public PredOp
 {
   protected: