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Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/misc.cc12
-rw-r--r--src/arch/arm/insts/static_inst.cc23
2 files changed, 22 insertions, 13 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 7d383a87a..c40b6711f 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +39,7 @@
*/
#include "arch/arm/insts/misc.hh"
+#include "cpu/reg_class.hh"
std::string
MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -48,17 +50,17 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
ss << ", ";
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
- int idx = srcRegIdx(i);
- if (idx < Ctrl_Base_DepTag) {
+ RegIndex idx = srcRegIdx(i);
+ RegIndex rel_idx;
+ if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
continue;
}
- idx -= Ctrl_Base_DepTag;
- if (idx == MISCREG_CPSR) {
+ if (rel_idx == MISCREG_CPSR) {
ss << "cpsr";
foundPsr = true;
break;
}
- if (idx == MISCREG_SPSR) {
+ if (rel_idx == MISCREG_SPSR) {
ss << "spsr";
foundPsr = true;
break;
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 8306c620f..3ab7dfb0e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +46,7 @@
#include "base/loader/symtab.hh"
#include "base/condcodes.hh"
#include "base/cprintf.hh"
+#include "cpu/reg_class.hh"
namespace ArmISA
{
@@ -208,8 +210,11 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
void
ArmStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
- switch (reg) {
+ RegIndex rel_reg;
+
+ switch (regIdxToClass(reg, &rel_reg)) {
+ case IntRegClass:
+ switch (rel_reg) {
case PCReg:
ccprintf(os, "pc");
break;
@@ -226,12 +231,14 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
ccprintf(os, "r%d", reg);
break;
}
- } else if (reg < Ctrl_Base_DepTag) {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
- } else {
- reg -= Ctrl_Base_DepTag;
- assert(reg < NUM_MISCREGS);
- ccprintf(os, "%s", ArmISA::miscRegName[reg]);
+ break;
+ case FloatRegClass:
+ ccprintf(os, "f%d", rel_reg);
+ break;
+ case MiscRegClass:
+ assert(rel_reg < NUM_MISCREGS);
+ ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
+ break;
}
}