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-rw-r--r--src/arch/arm/insts/mem.cc16
-rw-r--r--src/arch/arm/insts/mem.hh16
2 files changed, 32 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index ea98771e0..6cbe08ac8 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -43,9 +43,25 @@
#include "arch/arm/insts/mem.hh"
#include "base/loader/symtab.hh"
+using namespace std;
+
namespace ArmISA
{
+string
+Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ss << ", [";
+ printReg(ss, base);
+ ss << "]";
+ return ss.str();
+}
+
void
Memory::printInst(std::ostream &os, AddrMode addrMode) const
{
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index e58005883..6ed99ba5b 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -47,6 +47,22 @@
namespace ArmISA
{
+class Swap : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ IntRegIndex op1;
+ IntRegIndex base;
+
+ Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
+ : PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), base(_base)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class Memory : public PredOp
{
public: