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-rw-r--r--src/arch/arm/insts/sve_macromem.hh45
1 files changed, 35 insertions, 10 deletions
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index a31af9b92..b365dcb4b 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -46,7 +46,8 @@
namespace ArmISA {
template <typename RegElemType, typename MemElemType,
- template <typename, typename> class MicroopType>
+ template <typename, typename> class MicroopType,
+ template <typename> class FirstFaultWritebackMicroopType>
class SveIndexedMemVI : public PredMacroOp
{
protected:
@@ -58,17 +59,22 @@ class SveIndexedMemVI : public PredMacroOp
public:
SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- uint64_t _imm)
+ uint64_t _imm, bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm)
{
bool isLoad = (__opClass == MemReadOp);
+ assert(!firstFault || isLoad);
int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
numMicroops = num_elems;
if (isLoad) {
- numMicroops++;
+ if (firstFault) {
+ numMicroops += 2;
+ } else {
+ numMicroops++;
+ }
}
microOps = new StaticInstPtr[numMicroops];
@@ -90,10 +96,16 @@ class SveIndexedMemVI : public PredMacroOp
*uop = new MicroopType<RegElemType, MemElemType>(
mnem, machInst, __opClass, _dest, _gp,
isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
- num_elems);
+ num_elems, firstFault);
+ }
+
+ if (firstFault) {
+ *uop = new FirstFaultWritebackMicroopType<RegElemType>(
+ mnem, machInst, __opClass, num_elems, this);
+ } else {
+ --uop;
}
- --uop;
(*uop)->setLastMicroop();
microOps[0]->setFirstMicroop();
@@ -130,7 +142,8 @@ class SveIndexedMemVI : public PredMacroOp
};
template <typename RegElemType, typename MemElemType,
- template <typename, typename> class MicroopType>
+ template <typename, typename> class MicroopType,
+ template <typename> class FirstFaultWritebackMicroopType>
class SveIndexedMemSV : public PredMacroOp
{
protected:
@@ -147,19 +160,25 @@ class SveIndexedMemSV : public PredMacroOp
SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
IntRegIndex _offset, bool _offsetIs32,
- bool _offsetIsSigned, bool _offsetIsScaled)
+ bool _offsetIsSigned, bool _offsetIsScaled,
+ bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset),
offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
offsetIsScaled(_offsetIsScaled)
{
bool isLoad = (__opClass == MemReadOp);
+ assert(!firstFault || isLoad);
int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
numMicroops = num_elems;
if (isLoad) {
- numMicroops++;
+ if (firstFault) {
+ numMicroops += 2;
+ } else {
+ numMicroops++;
+ }
}
microOps = new StaticInstPtr[numMicroops];
@@ -181,10 +200,16 @@ class SveIndexedMemSV : public PredMacroOp
*uop = new MicroopType<RegElemType, MemElemType>(
mnem, machInst, __opClass, _dest, _gp, _base,
isLoad ? (IntRegIndex) VECREG_UREG0 : _offset, _offsetIs32,
- _offsetIsSigned, _offsetIsScaled, i, num_elems);
+ _offsetIsSigned, _offsetIsScaled, i, num_elems, firstFault);
+ }
+
+ if (firstFault) {
+ *uop = new FirstFaultWritebackMicroopType<RegElemType>(
+ mnem, machInst, __opClass, num_elems, this);
+ } else {
+ --uop;
}
- --uop;
(*uop)->setLastMicroop();
microOps[0]->setFirstMicroop();