1 files changed, 89 insertions, 0 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 25e616e8e..60f00e438 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -117,6 +117,38 @@ ISA::clear()
 
     miscRegs[MISCREG_MPIDR] = 0;
 
+    // Reset values of PRRR and NMRR are implementation dependent
+
+    miscRegs[MISCREG_PRRR] =
+        (1 << 19) | // 19
+        (0 << 18) | // 18
+        (0 << 17) | // 17
+        (1 << 16) | // 16
+        (2 << 14) | // 15:14
+        (0 << 12) | // 13:12
+        (2 << 10) | // 11:10
+        (2 << 8)  | // 9:8
+        (2 << 6)  | // 7:6
+        (2 << 4)  | // 5:4
+        (1 << 2)  | // 3:2
+        0;          // 1:0
+    miscRegs[MISCREG_NMRR] =
+        (1 << 30) | // 31:30
+        (0 << 26) | // 27:26
+        (0 << 24) | // 25:24
+        (3 << 22) | // 23:22
+        (2 << 20) | // 21:20
+        (0 << 18) | // 19:18
+        (0 << 16) | // 17:16
+        (1 << 14) | // 15:14
+        (0 << 12) | // 13:12
+        (2 << 10) | // 11:10
+        (0 << 8)  | // 9:8
+        (3 << 6)  | // 7:6
+        (2 << 4)  | // 5:4
+        (0 << 2)  | // 3:2
+        0;          // 1:0
+
     //XXX We need to initialize the rest of the state.
 }
 
@@ -362,6 +394,63 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_DTLBIASID:
             tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
             return;
+          case MISCREG_V2PCWPR:
+          case MISCREG_V2PCWPW:
+          case MISCREG_V2PCWUR:
+          case MISCREG_V2PCWUW:
+          case MISCREG_V2POWPR:
+          case MISCREG_V2POWPW:
+          case MISCREG_V2POWUR:
+          case MISCREG_V2POWUW:
+            {
+              RequestPtr req = new Request;
+              unsigned flags;
+              BaseTLB::Mode mode;
+              Fault fault;
+              switch(misc_reg) {
+                  case MISCREG_V2PCWPR:
+                      flags = TLB::MustBeOne;
+                      mode = BaseTLB::Read;
+                      break;
+                  case MISCREG_V2PCWPW:
+                      flags = TLB::MustBeOne;
+                      mode = BaseTLB::Write;
+                      break;
+                  case MISCREG_V2PCWUR:
+                      flags = TLB::MustBeOne | TLB::UserMode;
+                      mode = BaseTLB::Read;
+                      break;
+                  case MISCREG_V2PCWUW:
+                      flags = TLB::MustBeOne | TLB::UserMode;
+                      mode = BaseTLB::Write;
+                      break;
+                  case MISCREG_V2POWPR:
+                  case MISCREG_V2POWPW:
+                  case MISCREG_V2POWUR:
+                  case MISCREG_V2POWUW:
+                      panic("Security Extensions not implemented!");
+              }
+              req->setVirt(0, val, 1, flags, tc->readPC());
+              fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
+              if (fault == NoFault) {
+                  miscRegs[MISCREG_PAR] =
+                      (req->getPaddr() & 0xfffff000) |
+                      (tc->getDTBPtr()->getAttr() );
+                  DPRINTF(MiscRegs,
+                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
+                          val, miscRegs[MISCREG_PAR]);
+              }
+              else {
+                  // Set fault bit and FSR
+                  FSR fsr = miscRegs[MISCREG_DFSR];
+                  miscRegs[MISCREG_PAR] =
+                      (fsr.ext << 6) |
+                      (fsr.fsHigh << 5) |
+                      (fsr.fsLow << 1) |
+                      0x1; // F bit
+              }
+              return;
+            }
         }
     }
     setMiscRegNoEffect(misc_reg, newVal);